Biblio

Emerging non-volatile memory technology enables non-volatile main memory (NVMM) that can provide larger capacity and better energy-saving opportunities than DRAMs. However, its non-volatility raises security concerns, where the data in NVMMs can be taken if the memory is stolen. Memory encryption protects the data by limiting it always stays encrypted outside the processor boundary. However, the decryption latency before the data being used by the processor brings new performance burdens. Unlike DRAM-based main memory, such performance overhead worsens on the NVMM due to the slow latency. In this paper, we will introduce optimizations that can be used to re-design the encryption scheme. In our tests, our two new designs, 3-level split counter mode encryption and 8-block split counter mode encryption, improved performance by 26% and 30% at maximum and by 8% and 9% on average from the original encryption scheme, split counter encryption.