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2020-08-10
Wu, Zhengze, Zhang, Xiaohong, Zhong, Xiaoyong.  2019.  Generalized Chaos Synchronization Circuit Simulation and Asymmetric Image Encryption. IEEE Access. 7:37989–38008.
Generalized chaos systems have more complex dynamic behavior than conventional chaos systems. If a generalized response system can be synchronized with a conventional drive system, the flexible control parameters and unpredictable synchronization state will increase significantly. The study first constructs a four-dimensional nonlinear dynamic equation with quadratic variables as a drive system. The numerical simulation and analyses of the Lyapunov exponent show that it is also a chaotic system. Based on the generalized chaos synchronization (GCS) theory, a four-dimensional diffeomorphism function is designed, and the corresponding GCS response system is generated. Simultaneously, the structural and synchronous circuits of information interaction and control are constructed with Multisim™ software, with the circuit simulation resulting in a good agreement with the numerical calculations. In order to verify the practical effect of generalized synchronization, an RGB digital image secure communication scheme is proposed. We confuse a 24-bit true color image with the designed GCS system, extend the original image to 48-bits, analyze the scheme security from keyspace, key sensitivity and non-symmetric identity authentication, classical types of attacks, and statistical average from the histogram, image correlation. The research results show that this GCS system is simple and feasible, and the encryption algorithm is closely related to the confidential information, which can resist the differential attack. The scheme is suitable to be applied in network images or other multimedia safe communications.
2015-05-06
Yuankai Chen, Xuan Zeng, Hai Zhou.  2014.  Recovery-based resilient latency-insensitive systems. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014. :1-6.

As the interconnect delay is becoming a larger fraction of the clock cycle time, the conventional global stalling mechanism, which is used to correct error in general synchronous circuits, would be no longer feasible because of the expensive timing cost for the stalling signal to travel across the circuit. In this paper, we propose recovery-based resilient latency-insensitive systems (RLISs) that efficiently integrate error-recovery techniques with latency-insensitive design to replace the global stalling. We first demonstrate a baseline RLIS as the motivation of our work that uses additional output buffer which guarantees that only correct data can enter the output channel. However this baseline RLIS suffers from performance degradations even when errors do not occur. We propose a novel improved RLIS that allows erroneous data to propagate in the system. Equipped with improved queues that prevent accumulation of erroneous data, the improved RLIS retains the system performance. We provide theoretical study that analyzes the impact of errors on system performance and the queue sizing problem. We also theoretically prove that the improved RLIS performs no worse than the global stalling mechanism. Experimental results show that the improved RLIS has 40.3% and even 3.1% throughput improvements compared to the baseline RLIS and the infeasible global stalling mechanism respectively, with less than 10% hardware overhead.