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2017-11-01
Elsobky, Alaa Mahmoud, Farag, Abdelalim Kamal, Keshk, Arabi.  2016.  Efficient Implementation of McEliece Cryptosystem on Graphic Processing Unit. Proceedings of the 10th International Conference on Informatics and Systems. :247–253.
McEliece is a public-key cryptosystem based on error correcting codes. It has the ability to resist quantum-computer attacks which can break different modern public key cryptosystems such as RSA. Further more, it's encryption and decryption are very fast and have good characteristics for data parallel processing. Nowadays, modern graphic processing units (GPUs) are available in almost all hardware platforms. GPUs can comprise many compute cores which can process a huge data in parallel. In this paper, different implementations of McEliece cryptosystem are explored on NVIDIA GTX780 GPU using OpenCL framework. Our implementation results show that GPU is 331x faster than CPU when apply local memory with vector data-type to encrypt 216 messages.
2017-05-18
Park, Jungho, Jung, Wookeun, Jo, Gangwon, Lee, Ilkoo, Lee, Jaejin.  2016.  PIPSEA: A Practical IPsec Gateway on Embedded APUs. Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security. :1255–1267.

Accelerated Processing Unit (APU) is a heterogeneous multicore processor that contains general-purpose CPU cores and a GPU in a single chip. It also supports Heterogeneous System Architecture (HSA) that provides coherent physically-shared memory between the CPU and the GPU. In this paper, we present the design and implementation of a high-performance IPsec gateway using a low-cost commodity embedded APU. The HSA supported by the APUs eliminates the data copy overhead between the CPU and the GPU, which is unavoidable in the previous discrete GPU approaches. The gateway is implemented in OpenCL to exploit the GPU and uses zero-copy packet I/O APIs in DPDK. The IPsec gateway handles the real-world network traffic where each packet has a different workload. The proposed packet scheduling algorithm significantly improves GPU utilization for such traffic. It works not only for APUs but also for discrete GPUs. With three CPU cores and one GPU in the APU, the IPsec gateway achieves a throughput of 10.36 Gbps with an average latency of 2.79 ms to perform AES-CBC+HMAC-SHA1 for incoming packets of 1024 bytes.