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2018-04-02
Schürmann, D., Zengen, G. V., Priedigkeit, M., Wolf, L..  2017.  \#x003BC;DTNSec: A Security Layer for Disruption-Tolerant Networks on Microcontrollers. 2017 16th Annual Mediterranean Ad Hoc Networking Workshop (Med-Hoc-Net). :1–7.

We introduce $μ$DTNSec, the first fully-implemented security layer for Delay/Disruption-Tolerant Networks (DTN) on microcontrollers. It provides protection against eavesdropping and Man-in-the-Middle attacks that are especially easy in these networks. Following the Store-Carry-Forward principle of DTNs, an attacker can simply place itself on the route between source and destination. Our design consists of asymmetric encryption and signatures with Elliptic Curve Cryptography and hardware-backed symmetric encryption with the Advanced Encryption Standard. $μ$DTNSec has been fully implemented as an extension to $μ$DTN on Contiki OS and is based on the Bundle Protocol specification. Our performance evaluation shows that the choice of the curve (secp128r1, secp192r1, secp256r1) dominates the influence of the payload size. We also provide energy measurements for all operations to show the feasibility of our security layer on energy-constrained devices.

2017-11-03
Shwartz, O., Birk, Y..  2016.  SDSM: Fast and scalable security support for directory-based distributed shared memory. 2016 IEEE International Conference on the Science of Electrical Engineering (ICSEE). :1–5.

Secure computation is increasingly required, most notably when using public clouds. Many secure CPU architectures have been proposed, mostly focusing on single-threaded applications running on a single node. However, security for parallel and distributed computation is also needed, requiring the sharing of secret data among mutually trusting threads running in different compute nodes in an untrusted environment. We propose SDSM, a novel hardware approach for providing a security layer for directory-based distributed shared memory systems. Unlike previously proposed schemes that cannot maintain reasonable performance beyond 32 cores, our approach allows secure parallel applications to scale efficiently to thousands of cores.