Biblio

We show that a new type of dielectric cavity featuring deep sub-wavelength light confinement allows a significant speedup of all-optical signal processing functionalities, without compromising the energy efficiency. The effect is due to enhanced diffusion dynamics in an unconventional geometry.

In this study, the effect of surface treatment on the boding strength between Quad flat package (QFP) and quartz was investigated for establishing a QFP/quartz glass bonding technique. This bonding technique is necessary to prevent bond failure at the nano-artifact metrics (NAM) chip and adhesive interface against physical attacks such as counterfeiting and tampering of edge AI devices that use NAM chips. Therefore, we investigated the relationship between surface roughness and tensile strength by applying surface treatments such as vacuum ultraviolet (VUV) and Ar/O2 plasma. All QFP/quartz glass with surface treatments such as VUV and Ar/O2 plasma showed increased bond strength. Surface treatment and bonding technology for QFP and quartz glass were established to realize NAM chip mounting.

In this work, we have proposed a state-of-the-art face logging system that detects and logs high quality cropped face images of the people in real-time for security applications. Multiple strategies based on resolution, velocity and symmetry of faces have been applied to obtain best quality face images. The proposed system handles the issue of motion blur in the face images by determining the velocities of the detections. The output of the system is the face database, where four faces for each detected person are stored along with the time stamp and ID number tagged to it. The facial features are extracted by our system, which are used to search the person-of-interest instantly. The proposed system has been implemented in a docker container environment on two edge devices: the powerful NVIDIA Jetson TX2 and the cheaper NVIDIA Jetson N ano. The light and fast face detector (LFFD) used for detection, and ResN et50 used for facial feature extraction are optimized using TensorRT over these edge devices. In our experiments, the proposed system achieves the True Acceptance Rate (TAR) of 0.94 at False Acceptance Rate (FAR) of 0.01 while detecting the faces at 20–30 FPS on NVIDIA Jetson TX2 and about 8–10 FPS on NVIDIA Jetson N ano device. The advantage of our system is that it is easily deployable at multiple locations and also scalable based on application requirement. Thus it provides a realistic solution to face logging application as the query or suspect can be searched instantly, which may not only help in investigation of incidents but also in prevention of untoward incidents.

Vectorless integrity verification is becoming increasingly critical to robust design of nanoscale power delivery networks (PDNs). To dramatically improve efficiency and capability of vectorless integrity verifications, this paper introduces a scalable multilevel integrity verification framework by leveraging a hierarchy of almost linear-sized spectral power grid sparsifiers that can well retain effective resistances between nodes, as well as a recent graph-theoretic algebraic multigrid (AMG) algorithmic framework. As a result, vectorless integrity verification solution obtained on coarse level problems can effectively help find the solution of the original problem. Extensive experimental results show that the proposed vectorless verification framework can always efficiently and accurately obtain worst-case scenarios in even very large power grid designs.

Multi-state logic presents a promising avenue for more-than-Moore scaling, since efficient implementation of multi-valued logic (MVL) can significantly reduce switching and interconnection requirements and result in significant benefits compared to binary CMOS. So far, traditional approaches lag behind binary CMOS due to: (a) reliance on logic decomposition approaches [4][5][6] that result in many multi-valued minterms [4], complex polynomials [5], and decision diagrams [6], which are difficult to implement, and (b) emulation of multi-valued computation and communication through binary switches and medium that require data conversion, and large circuits. In this paper, we propose a fundamentally different approach for MVL decomposition, merging concepts from data science and nanoelectronics to tackle the problems, (a) First, we do linear regression on all inputs and outputs of a multivalued function, and find an expression that fits most input and output combinations. For unmatched combinations, we do successive regressions to find linear expressions. Next, using our novel visual pattern matching technique, we find conditions based on input and output conditions to select each expression. These expressions along with associated selection criteria ensure that for all possible inputs of a specific function, correct output can be reached. Our selection of regression model to find linear expressions, coefficients and conditions allow efficient hardware implementation. We discuss an approach for solving problem (b) and show an example of quaternary sum circuit. Our estimates show 65.6% saving of switching components compared with a 4-bit CMOS adder.