Biblio

In signed directed graph (SDG) fault diagnosis model, only single fault can be diagnosed. In order to meet the requirements of multiple faults diagnosis, in this paper, improved signed directed graph (ISDG) fault diagnosis model was proposed. The logic and influence between nodes were included in ISDG model. With ISDG model, complex logic can be shown, multiple faults can be diagnosed and the optimal sequence can be determined. Two algorithms are proposed in this paper. One algorithm can obtain the multiple faults combine logic, and the other algorithm can obtain the optimal path of fault diagnosis. According to these two algorithms, the efficiency was improved and the cost was reduced in the multiple fault diagnosis process. Finally, the faults of an aircraft engine bleed system were diagnosed with the interactive algorithm. The proposed algorithms can obtain a diagnosis result effectively. The results of two cases prove that these algorithms can be used for multiple fault diagnosis.

Hardware implementations of cryptographic algorithms may leak information through numerous side channels, which can be used to reveal the secret cryptographic keys, and therefore compromise the security of the algorithm. Power Analysis Attacks (PAAs) [1] exploit the information leakage from the device's power consumption (typically measured on the supply and/or ground pins). Digital circuits consume dynamic switching energy when data propagate through the logic in each new calculation (e.g. new clock cycle). The average power dissipation of a design can be expressed by: Ptot(t) = α · (Pd(t) + Ppvt(t)) (1) where α is the activity factor (the probability that the gate will switch) and depends on the probability distribution of the inputs to the combinatorial logic. This induces a linear relationship between the power and the processed data [2]. Pd is the deterministic power dissipated by the switching of the gate, including any parasitic and intrinsic capacitances, and hence can be evaluated prior to manufacturing. Ppvt is the change in expected power consumption due to nondeterministic parameters such as process variations, mismatch, temperature, etc. In this manuscript, we describe the design of logic gates that induce data-independent (constant) α and Pd.