Visible to the public Biblio

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2020-09-08
Meenu, M, Raajan, N.R., Greeta, S.  2019.  Secured Transmission of Data Using Chaos in Wcdma Network. 2019 International Conference on Vision Towards Emerging Trends in Communication and Networking (ViTECoN). :1–5.
Spreading code assumes an indispensable work in WCDMA system. Every individual client in a cell is isolated by an exceptional spread code. PN grouping are commonly utilized in WCDMA framework. For example, Walsh codes or gold codes as spread code. Data received from WCDMA are transmitted using chaotic signal and that signal is generated by using logistic map. It is unsuitable to be utilized as spreading sequence. Using a threshold function the chaos signal is changed in the form of binary sequence. Consequently, QPSK modulation techniques is analyzed in W-CDMA downlink over Additive white Gaussian noise channel (AWGN) and Rayleigh multipath fading channel. The activity was assessed with the assistance of BER contrary to SNR utilizing parameters indicating the BER in low to high in SNR.
2019-10-08
Tripathi, S. K., Pandian, K. K. S., Gupta, B..  2018.  Hardware Implementation of Dynamic Key Value Based Stream Cipher Using Chaotic Logistic Map. 2018 2nd International Conference on Trends in Electronics and Informatics (ICOEI). :1104–1108.

In the last few decades, the relative simplicity of the logistic map made it a widely accepted point in the consideration of chaos, which is having the good properties of unpredictability, sensitiveness in the key values and ergodicity. Further, the system parameters fit the requirements of a cipher widely used in the field of cryptography, asymmetric and symmetric key chaos based cryptography, and for pseudorandom sequence generation. Also, the hardware-based embedded system is configured on FPGA devices for high performance. In this paper, a novel stream cipher using chaotic logistic map is proposed. The two chaotic logistic maps are coded using Verilog HDL and implemented on commercially available FPGA hardware using Xilinx device: XC3S250E for the part: FT256 and operated at frequency of 62.20 MHz to generate the non-recursive key which is used in key scheduling of pseudorandom number generation (PRNG) to produce the key stream. The realization of proposed cryptosystem in this FPGA device accomplishes the improved efficiency equal to 0.1186 Mbps/slice. Further, the generated binary sequence from the experiment is analyzed for X-power, thermal analysis, and randomness tests are performed using NIST statistical.