Biblio

Wide bandgap power semiconductors are key enablers for increasing the power density of switch-mode power supplies. However, they require new gate drive technologies. This paper examines and characterizes a fabricated gate-driver in a class-E resonant inverter. The gate-driver's total area of 1.2mm2 includes two high-voltage transistors for gate-driving, integrated complementary metal-oxide-semiconductor (CMOS) gate-drivers, high-speed floating level-shifter and reset circuitry. A prototype printed circuit board (PCB) was designed to assess the implications of an electrostatic discharge (ESD) diode, its parasitic capacitance and package bondwire connections. The parasitic capacitance was estimated using its discharge time from an initial voltage and the capacitance is 56.7 pF. Both bondwires and the diode's parasitic capacitance is neglegible. The gate-driver's functional behaviour is validated using a parallel LC resonant tank resembling a self-oscillating gate-drive. Measurements and simulations show the ESD diode clamps the output voltage to a minimum of -2V.

We propose a crypto-aided Bayesian detection framework for detecting false data in short messages with low overhead. The proposed approach employs the Bayesian detection at the physical layer in parallel with a lightweight cryptographic detection, followed by combining the two detection outcomes. We develop the maximum a posteriori probability (MAP) rule for combining the cryptographic and Bayesian detection outcome, which minimizes the average probability of detection error. We derive the probability of false alarm and missed detection and discuss the improvement of detection accuracy provided by the proposed method.