Biblio

Smart grid is the key infrastructure of the country, and its network security is an important link to ensure the national important infrastructure security. SOC as a secure operation mechanism for adaptive and continuous improvement of information security, it is practically significant to address the challenge to the network security of the smart grid. Based on the analysis of the technical characteristics and security of smart grid, and taking a grid enterprise smart grid as an example, we propose the design scheme and implementation plan of smart grid SOC platform. Experimental results show that the platform we designed can meet the performance requirements, it also meets the requirements of real-time storage of behavioral data and provides support for interactive analysis and batch analysis.

Security concerns for field-programmable gate array (FPGA) applications and hardware are evolving as FPGA designs grow in complexity, involve sophisticated intellectual properties (IPs), and pass through more entities in the design and implementation flow. FPGAs are now routinely found integrated into system-on-chip (SoC) platforms, cloud-based shared computing resources, and in commercial and government systems. The IPs included in FPGAs are sourced from multiple origins and passed through numerous entities (such as design house, system integrator, and users) through the lifecycle. This paper thoroughly examines the interaction of these entities from the perspective of the bitstream file responsible for the actual hardware configuration of the FPGA. Five stages of the bitstream lifecycle are introduced to analyze this interaction: 1) bitstream-generation, 2) bitstream-at-rest, 3) bitstream-loading, 4) bitstream-running, and 5) bitstream-end-of-life. Potential threats and vulnerabilities are discussed at each stage, and both vendor-offered and academic countermeasures are highlighted for a robust and comprehensive security assurance.