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2018-06-07
Bresch, C., Michelet, A., Amato, L., Meyer, T., Hély, D..  2017.  A red team blue team approach towards a secure processor design with hardware shadow stack. 2017 IEEE 2nd International Verification and Security Workshop (IVSW). :57–62.

Software attacks are commonly performed against embedded systems in order to access private data or to run restricted services. In this work, we demonstrate some vulnerabilities of commonly use processor which can be leveraged by hackers to attack a system. The targeted devices are based on open processor architectures OpenRISC and RISC-V. Several software exploits are discussed and demonstrated while a hardware countermeasure is proposed and validated on OpenRISC against Return Oriented Programming attack.

2015-05-05
Elwell, J., Riley, R., Abu-Ghazaleh, N., Ponomarev, D..  2014.  A Non-Inclusive Memory Permissions architecture for protection against cross-layer attacks. High Performance Computer Architecture (HPCA), 2014 IEEE 20th International Symposium on. :201-212.

Protecting modern computer systems and complex software stacks against the growing range of possible attacks is becoming increasingly difficult. The architecture of modern commodity systems allows attackers to subvert privileged system software often using a single exploit. Once the system is compromised, inclusive permissions used by current architectures and operating systems easily allow a compromised high-privileged software layer to perform arbitrary malicious activities, even on behalf of other software layers. This paper presents a hardware-supported page permission scheme for the physical pages that is based on the concept of non-inclusive sets of memory permissions for different layers of system software such as hypervisors, operating systems, and user-level applications. Instead of viewing privilege levels as an ordered hierarchy with each successive level being more privileged, we view them as distinct levels each with its own set of permissions. Such a permission mechanism, implemented as part of a processor architecture, provides a common framework for defending against a range of recent attacks. We demonstrate that such a protection can be achieved with negligible performance overhead, low hardware complexity and minimal changes to the commodity OS and hypervisor code.