Skip to Main Content Area
CPS-VO
Contact Support
Browse
Calendar
Announcements
Repositories
Groups
Search
Search for Content
Search for a Group
Search for People
Search for a Project
Tagcloud
› Go to login screen
Not a member?
Click here to register!
Forgot username or password?
Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
microprocessor chips
biblio
An Orthogonal Algorithm for Key Management in Hardware Obfuscation
Submitted by grigby1 on Mon, 11/02/2020 - 12:28pm
member leakage attack
supply chain management
Supply Chain
semiconductor chips
security
reverse engineering
Resiliency
resilience
pubcrawl
Protocols
policy-based governance
partnership organization
orthogonal obfuscation algorithm
Orthogonal obfuscation
orthogonal matrix
microprocessor chips
authenticate obfuscation keys
Licenses
IP piracy attacks
IP piracy
IP networks
IP cores
intellectual property security
intellectual property piracy attacks
integrated circuits
integrated circuit design
industrial property
Hardware Security
Hardware
copy protection
composability
biblio
A Graph Theory Approach towards IJTAG Security via Controlled Scan Chain Isolation
Submitted by grigby1 on Mon, 11/02/2020 - 12:28pm
Registers
IJTAG network
IJTAG security
Instruments
intellectual property security
isolation signals
microprocessor chips
on-chip access
on-chip instruments
policy-based governance
power consumption
pubcrawl
IJTAG
resilience
Resiliency
scan chain
security
security of data
system-on-chip
system-on-chip designs
third party intellectual property providers
unauthorized user access
untrusted sources
Diagnosis
Clocks
Complexity theory
composability
controlled scan chain isolation
data integrity
Data Integrity Attacks
data manipulation
data protection scheme
data sniffing
debug
design for test
authorisation
electronic design automation
embedded instruments
embedded systems
graph coloring problem
graph colouring
graph theory approach
hidden test-data registers
IEEE standards
IEEE Std 1687
IEEE Std. 1687
biblio
Design and Analysis of SIC: A Provably Timing-Predictable Pipelined Processor Core
Submitted by grigby1 on Mon, 10/05/2020 - 2:00pm
SIC
worst-case execution time
WCET analysis
WCET
timing-predictable pipelined processor core
timing predictability
timing compositionality
timing anomalies
timing
Task Analysis
strictly in-order core
standard in-order pipeline design
Silicon carbide
Compositionality
real-time systems
pubcrawl
pipelining
Pipelines
pipeline processing
multiprocessing systems
multicore timing analysis
Multicore processing
multi-core
monotonicity
microprocessor chips
Hardware
biblio
Mitigating JTAG as an Attack Surface
Submitted by grigby1 on Fri, 08/28/2020 - 11:51am
private instructions
JTAG test access ports
JTAG-based debug
key registers
key systems
materiel availability issues
Metrics
microprocessor chips
on-chip embedded instrumentation
JTAG interface
pubcrawl
resilience
Resiliency
reverse engineering
Scalability
security
standard test access port
system memory
Cryptography
authorisation
BIT
boundary scan
boundary scan architecture
boundary scan testing
Built-In Test
chip lock
computer debugging
attack surface
debug architectures
depot system repair
embedded systems
firmware
IEEE 1149.1
IEEE standards
joint test action group standards
JTAG
biblio
More Secure Collaborative APIs Resistant to Flush+Reload and Flush+Flush Attacks on ARMv8-A
Submitted by grigby1 on Fri, 08/14/2020 - 11:44am
ARMv8-A processor
application programming interface
tablets
suspected Flush+Reload
static code analysis schemes
secure collaborative API
obfuscation techniques
mobile phones
Flush+Reload attack
Flush+Flush cache attacks
Flush+Flush attack
flush operation API
Collabo rative API
security of data
ARMv8 A
Compositionality
application program interfaces
APIs
program diagnostics
performance evaluation
cache storage
mobile computing
microprocessor chips
Resiliency
resilience
pubcrawl
biblio
Reusable intellectual property core protection for both buyer and seller
Submitted by grigby1 on Thu, 07/30/2020 - 2:05pm
intellectual property
seller watermark
scheduling phase
reusable intellectual property core protection
register allocation phase
latency overhead
IP seller
IP core protection
IP core design
design cost overhead
Consumer electronics
CE devices
buyer fingerprint
architectural synthesis process
ip protection
Watermarking
logic circuits
resource management
Metrics
Fingerprint recognition
Registers
composability
embedded systems
microprocessor chips
Resiliency
resilience
policy-based governance
Human Factors
Human behavior
pubcrawl
IP networks
logic design
biblio
POWERT Channels: A Novel Class of Covert CommunicationExploiting Power Management Vulnerabilities
Submitted by grigby1 on Thu, 07/16/2020 - 12:18pm
Resiliency
Power management
power management algorithms
power management vulnerabilities
power system management
POWERT channel capacity
pubcrawl
representative commercial systems
resilience
power headroom modulation
resource allocation
Runtime
runtime power management
Scalability
Software
system-wide shared resource
tight power budget
application performance requirements
Power demand
power aware computing
multiprocessing systems
Monitoring
microprocessor chips
instantaneous power demand timely
Hardware
critical shared resource
covert communication
covert channels
control systems
Compositionality
composability
channel capacity
bit rate 121.6 bit/s
biblio
A hierarchical approach to self-test, fault-tolerance and routing security in a Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:44pm
packet-switching
local self-test manager
malformed packets
malicious denial-of-service attack
malicious external agent
microprocessor chips
multiprocessing systems
network bandwidth
network-on-chip
NoC
on-chip networks
packet switching
local router
power virus
routing agent
routing security
security concerns
sorting-based algorithm
telecommunication network routing
test algorithms
two-tier approach
two-tier solution
virtual channel flow control
virtual channels
deadlock-free properties
Scalability
resilience
Resiliency
Metrics
associated physical channels
bus interconnects
chip multiprocessors
communication efficiency
computer network reliability
computer network security
deadlock situation
network on chip security
denial-of-service attacks
external source
fault data
fault tolerant computing
fault-information
fault-tolerance aspects
fault-tolerant routing
flit-switching
hierarchical approach
internet
local processing element
biblio
Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
hardware trojan
Trojan horses
system-on-chip
semiconductor design
security
run time mitigation
performance degradation Hardware Trojan attacks
NoC
network-on-chip
multiprocessor system on chips
multiprocessing systems
MPSoC
microprocessor chips
integrated circuit design
performance evaluation
Router Architecture
pubcrawl
hardware security issues
Hardware
denial of service attack
Degradation
Cryptography
cryptographic modules
computer architecture
Buffer storage
bit shuffling mechanism
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Earthquake — A NoC-based optimized differential cache-collision attack for MPSoCs
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
programming flexibility
MPSoC configurations
MPSoC Glass
multiprocessing systems
network-on-chip
Network-on-Chip communication structure
NoC
on-chip connectivity
optimized differential cache-collision attacks
optimized variant
microprocessor chips
security concerns
Security NoC
system-on-chip
Systems-on-Chips
timing
Timing attack
timing measurements
Timing Side-channel Attack
cache location
network on chip security
Scalability
Resiliency
resilience
Metrics
attack efficiency
cache activity
cache line
pubcrawl
cache memories
cache storage
computer architecture
Cryptography
earthquake attack
Earthquakes
encryption
Glass
« first
‹ previous
1
2
3
4
5
next ›
last »