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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
network-on-chip
biblio
A New Hardware Logic Circuit for Evaluating Multi-Processor Chip Security
Submitted by grigby1 on Fri, 05/15/2020 - 12:30pm
manufacturing processes
research hotspots
replay-type hardware Trojan
on-chip systems
NoC vulnerability
NoC power consumption
NoC hardware security
NoC
new hardware logic circuit
network-on-chip
network throughput reduction
multiprocessor chip security
multiprocessing systems
pubcrawl
logic circuits
invasive software
inter-core interconnection method
Integrated circuit interconnections
defense strategies
communication performance optimization
benchmark test set
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Efficient Timing Channel Protection for Hybrid (Packet/Circuit-Switched) Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:29pm
Switching circuits
network transmission
network-on-chip
packet switching
packet switching NoC
packet-circuit-switched
security in NoC
Separate interface Hybrid
side-channel attacks
network routing
system security policy
TDM
Throughput
timing
timing channel
timing channel protection
timing characteristics
timing side channel
combined hybrid routers
network on chip security
Scalability
Resiliency
resilience
Metrics
channel attacks
circuit switching
circuit switching NoC
pubcrawl
conventional hybrid router
covert timing channel
hybrid network-on-chip
hybrid NoC
Integrated circuit modeling
MP-SoC
multiprocessing systems
multiprocessor system-on-chip
biblio
A Diffusional Schedule for Traffic Reducing on Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:29pm
Schedules
network on chip
network-on-chip
NoC activities
parallel processing
parallel task execution
power aware computing
Protocols
remote data access
long-distance data synchronization
scheduling
synchronisation
Synchronization
Task Analysis
task mapping algorithm
task schedule
task traffic reduction
traffic distribution
diffusional schedule
network on chip security
Scalability
Resiliency
resilience
Metrics
application-layer optimization
Coherence
diffusional pattern
pubcrawl
energy consumption
energy efficient task schedule
energy saving
energy.
inefficient task schedule strategy
latency
latency reduction
Load modeling
biblio
Towards the formal verification of security properties of a Network-on-Chip router
Submitted by grigby1 on Fri, 05/15/2020 - 12:29pm
IP networks
timing
security
Routing
NoC routing architectures
Network-on-Chip router
network-on-chip
network routing
MultiProcessors Systems-on-Chip
multiprocessing systems
model checking
pubcrawl
integrated circuit design
Hardware
formal verification
Cryptography
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Architecting a Secure Wireless Network-on-Chip
Submitted by grigby1 on Fri, 05/15/2020 - 12:29pm
network-on-chip connecting cores
WNoC
wireless sensor networks
Wireless communication
wireless channels
traditional wired NoC
telecommunication security
security
Scalability
Resiliency
resilience
pubcrawl
Protocols
point-to-point multihop signaling
one-hop broadcasts
on-chip systems
Bandwidth
network-on-chip
network on chip security
network interface
multiprocessing systems
Multiaccess communication
Metrics
latency constraints
Integrated circuit interconnections
integrated circuit design
faulty wireless components
fault tolerance
entire chip
energy benefits
electrical wires
Communication system security
biblio
Secure Network-on-Chip Architectures for MPSoC: Overview and Challenges
Submitted by grigby1 on Fri, 05/15/2020 - 12:29pm
multiprocessing systems
Trojan horses
security threat attacks
security
secure routing algorithms
secure routing algorithm
secure network-on-chip architectures
Routing
processing cores
NoC-based systems
NoC
network-on-chip
multiprocessor-based systems on chip
pubcrawl
MPSoC
Malicious-Tolerant Routing Algorithms
HT
hardware trojan
Hardware
data communication
computer architecture
Metrics
resilience
Resiliency
Scalability
network on chip security
biblio
Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks
Submitted by aekwall on Mon, 05/11/2020 - 11:09am
persistent jamming attack
internal hardware Trojans
jamming attack
low-power transceivers
ML classifiers
network-on-chip communications
NoC switches
nonscalable multihop data transmission paths
On chip interconnect
On chip security
on-chip data transfer
on-chip wireless medium
denial-of-service attacks
radio transceivers
radiofrequency interconnections
random burst error correction code
Switches
switching networks
WiNoC security
wired NoC architectures
wireless interconnection
Wireless NoC
wireless NoC architectures
network on chip security
system-on-chip
telecommunication security
learning (artificial intelligence)
Resiliency
pubcrawl
wireless sensor networks
Wireless communication
Metrics
machine learning
telecommunication network routing
telecommunication computing
radio networks
Scalability
DoS
Hardware Security
error correction codes
radiofrequency interference
DoS attack
Jamming
denial-of-service attack
machine learning classifier
HT
network-on-chip
data transfer security threats
biblio
Design and analysis of a mesh-based Adaptive Wireless Network-on Chips Architecture With Irregular Network Routing
Submitted by aekwall on Mon, 05/11/2020 - 11:09am
network-on-chip
Wires
Wireless Router
Wireless Network-on Chip
wireless network
Wireless communication
wireless channels
token sharing arrangement
Telephone sets
telecommunication traffic
Scalability
Resiliency
remote Network-on-Chip
remote information transmission
pubcrawl
Benchmark testing
Network-on Chip structures
network routing
network on chip security
MulticoreArchitecture
Metrics
metallic interface
mesh-based adaptive Wireless Network-on chips architecture
mesh topology
irregular Network routing
gainful remote handsets
core messages
computer architecture
Communication system security
biblio
Security Network On-Chip for Mitigating Side-Channel Attacks
Submitted by aekwall on Mon, 05/11/2020 - 11:08am
multiple countermeasures
compromised device
contemporary hardware threats
design complexity
electromagnetic analysis attacks
electromagnetic interference
hardware security threats
high-confidence security network on-chip
individual threats
machine learning security IC
malicious physical interference
modern ICs
attack-specific countermeasures
on-chip distribution networks
On-chip power delivery
on-chip voltage variations
operating device-under-attack
robust confidence security network on-chip
security networks
Side-channel attack
side-channel attack mitigation
strict performance requirements
trained ML ICs
network on chip security
timing
Scalability
learning (artificial intelligence)
Resiliency
pubcrawl
Metrics
machine learning
physical interaction
system-on-chip
system security
sensors
Attack detection
security of data
Hardware Security
side-channel attacks
integrated circuit design
data analysis
malicious activity
integrated circuits
network-on-chip
active attack
advance invasive attacks
advance noninvasive attacks
advanced technology nodes
biblio
Resilient Reorder Buffer Design for Network-on-Chip
Submitted by grigby1 on Fri, 03/27/2020 - 11:27am
Reorder Buffer
Network interfaces
network-on-chip
Network-on-Chip Advanced eXtensible Interface Network Interface block
parallel processing
policy-based governance
pubcrawl
random control logic
Registers
Metrics
resilience
Resiliency
resilient Reorder buffer design
Safe Coding
safe control logic design
safe ROB design
Safety
Table lookup
fault tolerance
buffer circuits
collaboration
control logic function
Diagnostic Coverage requirement
error correction codes
error detection
error detection code
error detection codes
area efficient safe design techniques
Fault tolerant systems
high performance computing systems
Human behavior
Human Factors
Industries
integrated circuit design
invariance checking
logic design
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