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Cyber-Physical Systems Virtual Organization
Read-only archive of site from September 29, 2023.
CPS-VO
Hardware Security Architecture
file
Managing Hardware Security in Three Dimensional Integrated Circuits
Submitted by Qiaoyan Yu on Wed, 01/08/2020 - 2:10pm. Contributors:
Qiaoyan Yu
Emre Salman
Project Slides
Hardware Security Architecture
Hardware Security Design
Systems
1717130
SaTC PI Meeting 2019
file
Language-Hardware Co-Design for Practical and Verifiable Information Flow Control
Submitted by edwardsuh on Wed, 01/08/2020 - 2:10pm. Contributors:
G. Edward Suh
Andrew C. Meyers
Project Slides
Formal Methods and Language-based Security
Hardware Security Architecture
Hardware Security Design
1513797
SaTC PI Meeting 2019
file
Invisible Shield Can Compression Harden Deep Neural Networks Universally Against Adversarial Attacks
Submitted by Wujie Wen on Wed, 01/08/2020 - 2:10pm. Contributor:
wujie wen
Project Slides
data science
Hardware Security Architecture
Hardware Security Design
1840813
SaTC PI Meeting 2019
file
Automatic Synthesis of Verifiably Secure Hardware Accelerators
Submitted by Zhiru Zhang on Wed, 01/08/2020 - 2:10pm. Contributors:
Zhiru Zhang
G. Edward Suh
Project Slides
Hardware Security Architecture
Hardware Security Design
1618275
SaTC PI Meeting 2019
file
Side Channels through Lower-Level Caches Attachs, Defenses and Security Metrics
Submitted by Dmitry Ponomarev on Tue, 01/07/2020 - 11:46am. Contributors:
Dmitry Ponomarev
Nael Abu-Ghazaleh
Project Slides
Hardware Security Architecture
Hardware Security Design
Systems
1422401
SaTC PI Meeting 2019
file
Practical Hardware-Assisted Always-On Malware Detection
Submitted by Nael Abu-Ghazaleh on Tue, 01/07/2020 - 11:46am. Contributors:
Nael Abu-Ghazaleh
Dmitry Ponomarev
Lei Yu
Project Slides
Hardware Security Architecture
Hardware Security Design
Systems
1619322
1617915
SaTC PI Meeting 2019
file
Efficient Hardware-Aware and Hardware-Enabled Algorithms for Secure In-Memory Databases
Submitted by Rajeev Balasubram... on Tue, 01/07/2020 - 11:46am. Contributor:
Rajeev Balasubramonian
Project Slides
Hardware Security Architecture
Hardware Security Design
Systems
1718834
SaTC PI Meeting 2019
file
TWC: Small: Side-Channels through Lower-Level Caches: Attacks, Defenses and Security Metrics
Submitted by Dmitry Ponomarev on Mon, 10/21/2019 - 12:29pm. Contributors:
Dmitry Ponomarev
Nael Abu-Ghazaleh
Posters
Hardware Security Architecture
Hardware Security Design
Systems
1422401
SaTC PI Meeting 2019
2019
NSF
U.S. Government
Poster
file
The Strength of Combined Distinguishers and Combined Side-Channel Attacks
Submitted by Selcuk Kose on Mon, 10/21/2019 - 12:29pm. Contributor:
Selcuk Kose
Posters
Hardware Security Architecture
Hardware Security Design
1929774
SaTC PI Meeting 2019
2019
NSF
U.S. Government
Poster
file
CRII: SaTC: Robust Design-for-Security (DFS) Architecture for Enabling Trust in Integrated Circuits (IC) Manufacturing and Test
Submitted by ujjwal.guin@aubur... on Mon, 10/21/2019 - 12:28pm. Contributor:
Ujjwal Guin
Posters
Hardware Security Architecture
Hardware Security Design
1755733
SaTC PI Meeting 2019
2019
NSF
U.S. Government
Poster
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