Biblio

Filters: Author is Qin, Y.  [Clear All Filters]
2021-03-22
Pitaval, R.-A., Qin, Y..  2020.  Grassmannian Frames in Composite Dimensions by Exponentiating Quadratic Forms. 2020 IEEE International Symposium on Information Theory (ISIT). :13–18.
Grassmannian frames in composite dimensions D are constructed as a collection of orthogonal bases where each is the element-wise product of a mask sequence with a generalized Hadamard matrix. The set of mask sequences is obtained by exponentiation of a q-root of unity by different quadratic forms with m variables, where q and m are the product of the unique primes and total number of primes, respectively, in the prime decomposition of D. This method is a generalization of a well-known construction of mutually unbiased bases, as well as second-order Reed-Muller Grassmannian frames for power-of-two dimension D = 2m, and allows to derive highly symmetric nested families of frames with finite alphabet. Explicit sets of symmetric matrices defining quadratic forms leading to constructions in non-prime-power dimension with good distance properties are identified.
2017-11-27
Qin, Y., Wang, H., Jia, Z., Xia, H..  2016.  A flexible and scalable implementation of elliptic curve cryptography over GF(p) based on ASIP. 2016 IEEE 35th International Performance Computing and Communications Conference (IPCCC). :1–8.

Public-key cryptography schemes are widely used due to their high level of security. As a very efficient one among public-key cryptosystems, elliptic curve cryptography (ECC) has been studied for years. Researchers used to improve the efficiency of ECC through point multiplication, which is the most important and complex operation of ECC. In our research, we use special families of curves and prime fields which have special properties. After that, we introduce the instruction set architecture (ISA) extension method to accelerate this algorithm (192-bit private key) and build an ECC\_ASIP model with six new ECC custom instructions. Finally, the ECC\_ASIP model is implemented in a field-programmable gate array (FPGA) platform. The persuasive experiments have been conducted to evaluate the performance of our new model in the aspects of the performance, the code storage space and hardware resources. Experimental results show that our processor improves 69.6% in the execution efficiency and requires only 6.2% more hardware resources.