Hao, Qiang, Xu, Dongdong, Zhang, Zhun, Wang, Jiqing, Le, Tong, Wang, Jiawei, Zhang, Jinlei, Liu, Jiakang, Ma, Jinhui, Wang, Xiang.
2022.
A Hardware-Assisted Security Monitoring Method for Jump Instruction and Jump Address in Embedded Systems. 2022 8th Annual International Conference on Network and Information Systems for Computers (ICNISC). :197–202.
With the development of embedded systems towards networking and intelligence, the security threats they face are becoming more difficult to prevent. Existing protection methods make it difficult to monitor jump instructions and their target addresses for tampering by attackers at the low hardware implementation overhead and performance overhead. In this paper, a hardware-assisted security monitoring module is designed to monitor the integrity of jump instructions and jump addresses when executing programs. The proposed method has been implemented on the Xilinx Kintex-7 FPGA platform. Experiments show that this method is able to effectively monitor tampering attacks on jump instructions as well as target addresses while the embedded system is executing programs.
Zhang, Zhun, Hao, Qiang, Xu, Dongdong, Wang, Jiqing, Ma, Jinhui, Zhang, Jinlei, Liu, Jiakang, Wang, Xiang.
2022.
Real-Time Instruction Execution Monitoring with Hardware-Assisted Security Monitoring Unit in RISC-V Embedded Systems. 2022 8th Annual International Conference on Network and Information Systems for Computers (ICNISC). :192–196.
Embedded systems involve an integration of a large number of intellectual property (IP) blocks to shorten chip's time to market, in which, many IPs are acquired from the untrusted third-party suppliers. However, existing IP trust verification techniques cannot provide an adequate security assurance that no hardware Trojan was implanted inside the untrusted IPs. Hardware Trojans in untrusted IPs may cause processor program execution failures by tampering instruction code and return address. Therefore, this paper presents a secure RISC-V embedded system by integrating a Security Monitoring Unit (SMU), in which, instruction integrity monitoring by the fine-grained program basic blocks and function return address monitoring by the shadow stack are implemented, respectively. The hardware-assisted SMU is tested and validated that while CPU executes a CoreMark program, the SMU does not incur significant performance overhead on providing instruction security monitoring. And the proposed RISC-V embedded system satisfies good balance between performance overhead and resource consumption.
