Biblio

In order to solve the problem of high data collision probability, high access delay and high-power consumption in random access process of power Internet of Things, an access scheme for large-scale micro-power wireless sensors based on slot-scheduling and hybrid mode is presented. This scheme divides time into different slots and designs a slot-scheduling algorithm according to network workload and power consumption. Sensors with different service priorities are arranged in different time slots for competitive access, using appropriate random-access mechanism. And rationally arrange the number of time slots and competing end-devices in different time slots. This scheme is able to meet the timeliness requirements of different services and reduce the overall network power consumption when dealing with random access scenarios of large-scale micro-power wireless sensor network. Based on the simulation results of actual scenarios, this access scheme can effectively reduce the overall power consumption of the network, and the high priority services can meet the timeliness requirements on the premise of lower power consumption, while the low priority services can further reduce power consumption.

Recently, code reuse attacks (CRAs) have emerged as a new class of ingenious security threatens. Attackers can utilize CRAs to hijack the control flow of programs to perform malicious actions without injecting any codes. Existing defenses against CRAs often incur high memory and performance overheads or require extending the existing processors' instruction set architectures (ISAs). To tackle these issues, we propose a hardware-based control flow integrity (CFI) that employs physical unclonable functions (PUF)-based linear encryption architecture (LEA) to protect against CRAs with negligible hardware extending and run time overheads. The proposed method can protect ret and indirect jmp instructions from return oriented programming (ROP) and jump oriented programming (JOP) without any additional software manipulations and extending ISAs. The pre-process will be conducted on codes once the executable binary is loaded into memory, and the real-time control flow verification based on LEA can be done while ret and jmp instructions are executed. Performance evaluations on benchmarks show that the proposed method only introduces 0.61% run-time overhead and 0.63% memory overhead on average.