Biblio

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2023-07-21
Zhou, Haosu, Lu, Wenbin, Shi, Yipeng, Liu, Zhenfu, Liu, Liu, Dong, Ningfei.  2022.  Constant False Alarm Rate Frame Detection Strategy for Terrestrial ASM/VDE Signals Received by Satellite. 2022 IEEE 5th International Conference on Electronics and Communication Engineering (ICECE). :29—33.
Frame detection is an important part of the reconnaissance satellite receiver to identify the terrestrial application specific messages (ASM) / VHF data exchange (VDE) signal, and has been challenged by Doppler shift and message collision. A constant false alarm rate (CFAR) frame detection strategy insensitive to Doppler shift has been proposed in this paper. Based on the double Barker sequence, a periodical sequence has been constructed, and differential operations have been adopted to eliminate the Doppler shift. Moreover, amplitude normalization is helpful for suppressing the interference introduced by message collision. Simulations prove that the proposed CFAR frame detection strategy is very attractive for the reconnaissance satellite to identify the terrestrial ASM/VDE signal.
2017-10-27
Gu, Peng, Li, Shuangchen, Stow, Dylan, Barnes, Russell, Liu, Liu, Xie, Yuan, Kursun, Eren.  2016.  Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges. Proceedings of the 26th Edition on Great Lakes Symposium on VLSI. :347–352.

3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks, hardware trojans, secure IC manufacturing and IP piracy. By utilizing intrinsic characteristics of 2.5D and 3D technologies, we propose novel opportunities in designing secure systems. We present: (i) a 3D architecture for shielding side-channel information; (ii) split fabrication using active interposers; (iii) circuit camouflage on monolithic 3D IC, and (iv) 3D IC-based security processing-in-memory (PIM). Advantages and challenges of these designs are discussed, showing that the new designs can improve existing countermeasures against security threats and further provide new security features.

2017-08-18
Gu, Peng, Li, Shuangchen, Stow, Dylan, Barnes, Russell, Liu, Liu, Xie, Yuan, Kursun, Eren.  2016.  Leveraging 3D Technologies for Hardware Security: Opportunities and Challenges. Proceedings of the 26th Edition on Great Lakes Symposium on VLSI. :347–352.

3D die stacking and 2.5D interposer design are promising technologies to improve integration density, performance and cost. Current approaches face serious issues in dealing with emerging security challenges such as side channel attacks, hardware trojans, secure IC manufacturing and IP piracy. By utilizing intrinsic characteristics of 2.5D and 3D technologies, we propose novel opportunities in designing secure systems. We present: (i) a 3D architecture for shielding side-channel information; (ii) split fabrication using active interposers; (iii) circuit camouflage on monolithic 3D IC, and (iv) 3D IC-based security processing-in-memory (PIM). Advantages and challenges of these designs are discussed, showing that the new designs can improve existing countermeasures against security threats and further provide new security features.