| Title | SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures |
| Publication Type | Conference Paper |
| Year of Publication | 2018 |
| Authors | Chittamuru, Sai Vineel Reddy, Thakkar, Ishan G, Bhat, Varun, Pasricha, Sudeep |
| Conference Name | Proceedings of the 55th Annual Design Automation Conference |
| Publisher | ACM |
| Conference Location | New York, NY, USA |
| ISBN Number | 978-1-4503-5700-5 |
| Keywords | composability, hardware security, Metrics, photonic NoCs, Process Variations, pubcrawl, Resiliency, signal processing security |
| Abstract | Photonic networks-on-chip (PNoCs) enable high bandwidth on-chip data transfers by using photonic waveguides capable of dense-wave-length-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation. A Hardware Trojan in a PNoC can manipulate the electrical driving circuit of its MRs to cause the MRs to snoop data from the neighboring wavelength channels in a shared photonic waveguide. This introduces a serious security threat. This paper presents a novel framework called SOTERIA+ that utilizes process variation based authentication signatures along with architecture-level enhancements to protect data in PNoC architectures from snooping attacks. Evaluation results indicate that our approach can significantly enhance the hardware security in DWDM-based PNoCs with minimal overheads of up to 10.6% in average latency and of up to 13.3% in energy-delay-product (EDP). |
| URL | http://doi.acm.org/10.1145/3195970.3196118 |
| DOI | 10.1145/3195970.3196118 |
| Citation Key | chittamuru_soteria:_2018 |
SOTERIA: Exploiting Process Variations to Enhance Hardware Security with Photonic NoC Architectures