| Title | A High Speed SM3 Algorithm Implementation for Security Chip |
| Publication Type | Conference Paper |
| Year of Publication | 2021 |
| Authors | Zang, Shiping, Zhao, Dongyan, Hu, Yi, Hu, Xiaobo, Gao, Ying, Du, Pengcheng, Cheng, Song |
| Conference Name | 2021 IEEE 5th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC) |
| Keywords | Clocks, composability, Conferences, Crypto, cryptography, Frequency synthesizers, high performance hash algorithm, high speed crypto chip, information technology, Metrics, Microelectronics, Microelectronics Security, Optimization, pubcrawl, resilience, Resiliency, SM3 Algorithm, Throughput |
| Abstract | High throughput of crypto circuit is critical for many high performance security applications. The proposed SM3 circuit design breaks the inherent limitation of the conventional algorithm flow by removing the "blocking point" on the critical path, and reorganizes the algebraic structure by adding four parallel compensation operations. In addition, the round expansion architecture, CSA (Carry Save Adder) and pre-calculation are also used in this design. Due to the optimization at both the algorithm level and the circuit level, the synthesized circuit of this design can reach maximum 415MHz operating clock frequency and 6.4Gbps throughput with SMIC 40nm high performance technology. Compared with the conventional implementation method, the throughput performance of the proposed SM3 circuit increases by 97.5% and the chip area of SM3 algorithm area is only increased by 16.2%. |
| DOI | 10.1109/IAEAC50856.2021.9390790 |
| Citation Key | zang_high_2021 |
A High Speed SM3 Algorithm Implementation for Security Chip