Biblio
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2021. Frequency Reconfigurable Microstrip Bandpass Filter Based on VO2. 2021 IEEE International Conference on Computer Science, Electronic Information Engineering and Intelligent Control Technology (CEI). :827–831.
Reconfigurability is very popular in advanced highly integrated wireless communication circuits and systems, which is valuable for mitigating spectrum congestion and reducing signal interference. To reduce interference and meet the different wireless standards in different countries, frequency reconfigurable filters are promising. Concurrently, due to the conductor and semiconductor properties of VO2 at different temperatures or pressures, the phase transition characteristics of new material VO2 are applied to reconfigurable filters. This paper mainly discusses the application of phase transition characteristics of VO2 materials in filter design and proposes a frequency reconfigurable microstrip bandpass filter based on VO2 materials, in which the microstrip filter adopts the design form of end coupling. Through theoretical calculation, data analysis, and the establishment of the equivalent model of VO2 phase transition, a related design is proposed. An end-coupled microband bandpass filter centered at a reconfigurable frequency (6 GHz to 6.5 GHz) with fractional bandwidth of 2.8% has been designed, which shows consistent match with the expected ones and verify the validity of the proposed method.
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2021. A High Speed SM3 Algorithm Implementation for Security Chip. 2021 IEEE 5th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC). 5:915–919.
High throughput of crypto circuit is critical for many high performance security applications. The proposed SM3 circuit design breaks the inherent limitation of the conventional algorithm flow by removing the "blocking point" on the critical path, and reorganizes the algebraic structure by adding four parallel compensation operations. In addition, the round expansion architecture, CSA (Carry Save Adder) and pre-calculation are also used in this design. Due to the optimization at both the algorithm level and the circuit level, the synthesized circuit of this design can reach maximum 415MHz operating clock frequency and 6.4Gbps throughput with SMIC 40nm high performance technology. Compared with the conventional implementation method, the throughput performance of the proposed SM3 circuit increases by 97.5% and the chip area of SM3 algorithm area is only increased by 16.2%.