Visible to the public High-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring

TitleHigh-speed Hardware Accelerator for Trace Decoding in Real-Time Program Monitoring
Publication TypeConference Paper
Year of Publication2021
AuthorsHoppe, Augusto, Becker, Jürgen, Kastensmidt, Fernanda Lima
Conference Name2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS)
KeywordsARM Cortex-A9, Control Flow Monitoring, CoreSight, Decoding, Focusing, FPGA, Hardware, Metrics, multicore computing security, Multicore processing, Online Trace, Program processors, pubcrawl, Real-time Systems, resilience, Resiliency, Safety, Scalability
AbstractMulticore processors are currently the focus of new and future critical-system architectures. However, they introduce new problems in regards to safety and security requirements. Real-time control flow monitoring techniques were proposed as solutions to detect the most common types of program errors and security attacks. We propose a new way to use the latest debug and trace architectures to achieve full and isolated real-time control flow monitoring. We present an online trace decoder FPGA component as a solution in the search for scalable and portable monitoring architectures. Our FPGA accelerator achieves real-time CPU monitoring with only 8% of used resources in a Zynq-7000 FPGA.
DOI10.1109/LASCAS51355.2021.9459137
Citation Keyhoppe_high-speed_2021