DATE D2 - CfP
CALL FOR PAPERS DATE 2015
Topic Track: D2 System Design, High-Level Synthesis and Optimization
DATE (Design, Automation & Test in Europe) Conference
Grenoble, France, 9-13 March, 2015
http://www.date-conference.com
- Deadline Paper Submission: Sunday September 14, 2014
- Notification of Acceptance: Friday November 07, 2014
- Camera-Ready Paper Due: Friday November 28, 2014
DATE conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in the hardware and software design, test and manufacturing of electronic circuits and systems. It puts strong emphasis on ICs/SoCs, reconfigurable hardware and embedded systems, including embedded software.
The five-day event consists of a conference with plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days and a track for executives. The scientific conference is complemented by a commercial exhibition showing the state-of-the-art in design and test tools, methodologies, IP and design services, reconfigurable and other hardware platforms, embedded software, and (industrial) design experiences from different application domains, e.g. automotive, wireless, telecom and multimedia applications. The organisation of user group meetings, fringe meetings, a university booth, a PhD forum, vendor presentations and social events offers a wide variety of extra opportunities to meet and exchange information on relevant issues for the design and test community. Special space will also be allocated for EU funded projects to show their results.
You are invited to submit your research contributions to the topic
D2: System Design, High-Level Synthesis and Optimization
D2 is about high-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for hardware/software co-design and partitioning; control and data flow analysis; hardware/software interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation and binding techniques; multi-objective optimization techniques (performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; HW/SW design patterns for multi-core system on chip (MPSoC) and distributed, networked embedded systems; system-level design of heterogeneous computing systems.
D2 Technical Program Committee:
- Andreas Herkersdorf, Technische Universitat Munchen, DE (Chair),
- Nikil Dutt, University of California Irvine, US (Co-Chair),
- Kubilay Atasu, IBM Research, CH,
- Alberto A. del Barrio, Universidad Complutense de Madrid, ES,
- Lars Bauer, Karlsruhe Institute of Technology, DE,
- Kim N. Gruttner, OFFIS, DE,
- Soonhoi Ha, Seoul National University, KR,
- Yuko Hara-Azumi, Tokyo Institute of Technology, JP,
- Jan Madsen, Technical University of Denmark, DK,
- Donatella Sciuto, Politecnico di Milano, IT,
- Todor Stefanov, Leiden University, NL,
- Jurgen Teich, Universitat Erlangen-Nurnberg, DE,
- David Thomas, Imperial College London, UK,
- Yosinori Watanabe, Cadence, US,
- Jason Xue Chun, City University of Hong Kong, HK.