RAPIDO'16

8th Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO'16)

In conjunction with International Conference on High-Performance and Embedded Architectures and Compilers (Hipeac 2016)

Topics of interest include, but are not limited to:

• Rapid simulation techniques especially those targeted at new architectures: Multi-cores, 3D-architectures, FPGA based heterogeneous Multi-cores/MPSoC, ...etc;
• Variability and power/energy consumption in performance estimation and simulation techniques;
• High-level abstraction modeling, e.g., Transactional Level Modeling (TLM), Analytical Modeling, Trace-Driven Simulation, ...etc;
• Rapid design space exploration (DSE) for heterogeneous and embedded systems;
• Dynamic binary translation for fast simulation and DSE;
• Experience reports using existing simulators;
• Benchmarking and simulator validation.

Organizing Committee

• Gianluca Palermo, Politecnico di Milano, Italy
• Daniel Gracia Perez, Thales Research & Technology, France
• Morteza Biglari Abhari, The University of Auckland, New Zealand
• Daniel Chillet, Universite de Rennes 1, France
• Smail Niar, University of Valenciennes and Hainaut-Cambresis, France
• Adam Morawiec, ECSI, France

Contacts:

• Gianluca Palermo (gianluca dot palermo at polimi dot it), Politecnico di Milano, Italy
• Daniel Gracia Perez (daniel dot gracia-perez at thalesgroup dot com), Thales Research & Technology, France