Call for Abstracts: ICCAD'15 Workshop on "Towards Efficient Computing in the Dark Silicon Era" - Extended Deadline

Extended Abstract Submission Deadline: October 02, 2015

ICCAD'15 Workshop on "Towards Efficient Computing in the Dark Silicon Era"

Thursday, November 5, 2015 | Doubletree Hotel, Austin, TX, USA

Workshop Site: https://wp.nyu.edu/iccad_darksil_workshop/
Submission Page: https://easychair.org/conferences/?conf=ecds2015

This workshop is organized as a collocated even at the International Conference on Computer-Aided Design (ICCAD), November 2-6, 2015: http://iccad.com/

General Description:

Supply voltage scaling has slowed down in the leakage dominated nanometer era because a lower supply voltage necessitates a lower threshold voltage (for iso-performance), which in turn exponentially increases leakage power consumption. As a result, although we can integrate more transistors per unit area with technology scaling, the switching power per transistor does not scale commensurately. Coupled with the physical limits imposed by device packaging and cooling technology on the peak power and peak power density, this results in the so-called dark silicon problem, i.e., not all parts of the chip can be simultaneously powered on at nominal voltage. It is projected that at the 8 nm technology node, more than half of the chip area will be dark. The emergence of dark silicon introduces several new challenges for EDA and low-power design research across design abstractions (ranging from devices and circuits to micro-architecture and the system level), for instance, how to best utilize the abundance of (potentially dark) transistors, both in terms of design time provisioning and run-time management, so as to improve quality metrics (performance, reliability, lifetime, etc.) within peak power and thermal constraints. The EDA and architecture communities have potentially much to contribute here because dark silicon also opens up a vast design space of potential solutions and navigating this design space in a computationally efficient way to narrow down on the most promising solutions is an important challenge. Dark Silicon processors are envisaged to be designed different from the largely homogeneous multi-cores commercially available today and will instead feature a heterogeneous mix of computing and communication resources to achieve higher performance and better power/energy/thermal efficiency. The heterogeneous system architecture (HAS) is becoming the norm for different computing platforms, including servers and mobile devices. For this, general purpose CPUs can be paired with additional processing units such as vector units (AVX and SSE), GPUs, FPGAs, and other custom hardware.

This workshop is intended to provide a common platform for EDA experts, computer architects, and system designers to discuss their vision and perspectives on the dark silicon problem and the role of heterogeneous computing to significantly improve the computing efficiency of next-generation on-chip systems in the dark silicon era.

Topics of interest include, but are not limited to:

1. Exploiting new architectural opportunities in next generation dark silicon chips including but not limited to heterogeneous, reconfigurable, GPU, and application-specific design paradigms and industrial trends by Intel, IBM, AMD, and Nvidia.
2. Efficient and scalable run-time dark silicon management under power and thermal considerations while jointly optimizing for quality metrics including performance, reliability, lifetime, etc.
3. Opportunities and challenges in gray silicon (e.g. using near-threshold voltage computing) including analysis, modeling, variability and reliability challenges.
4. Programming models (OpenCL, CUDA), compiler and operating system support for dark silicon chips with specialized resources, adaptive modes of parallelism, etc.
5. Hardware/Software co-synthesis and implementation issues on HSA.
6. On-chip communication architectures for dark silicon chips, e.g., efficient data transfer mechanisms between different parts of the chip.
7. Integration of new device technologies (steep-slope devices, nano-electromechanical switches, etc.) and cooling technologies (e.g., phase change materials) and their interaction with dark silicon.
8. Killer application domains (mobile, big data, enterprise, etc.) for heterogeneous dark silicon chips: shrinking die size versus more (dark) transistors in the same area.

• Submission deadline: October 02, 2015
• Author notification: October 04, 2015
• Camera-ready version: October 10, 2015
• Early Registration: October 05, 2015
• Workshop: November 05, 2015

Submission Guidelines:

• Abstract submissions for both research and work-in-progress works are welcome. The abstracts should describe original research content and interesting technical aspects of real-world applications.
• All abstracts should be submitted in PDF format through the EasyChair system: https://easychair.org/conferences/?conf=ecds2015
• Submissions must be limited to 1 or 2 pages, single-spaced, double-column IEEE format with 9- or 10-point fonts.
• All the accepted abstracts will be made available online on the workshop webpage.

Presentation Format:

• Authors of the accepted abstracts will have 1-2 minutes for the idea pitch talks followed by a poster session for detailed technical discussions.

Organizers:

• Muhammad Shafique, KIT, Germany (muhammad.shafique@kit.edu)
• Siddharth Garg, NYU, USA (sg175@nyu.edu)
• Mustafa Ozdal, Bilkent University, Turkey (mustafa.ozdal@cs.bilkent.edu.tr)
• Gi-Joon Nam, IBM USA (gnam@us.ibm.com)