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Submitted by Anonymous on Thu, 02/11/2016 - 5:10pm
Jul 18, 2016 7:00 am - Jul 22, 2016 6:00 pm CEST

The 8th International Workshop on Dependable Many-Core Computing (DMCC 2016)

As part of The International Conference on High Performance Computing & Simulation (HPCS 2016)

SCOPE AND OBJECTIVES

Computing systems with a large number of processing units are increasingly common, both in the form of processors employing multiple execution cores (e.g., multi-core CPUs, GPUs), or computing clusters with a large number of nodes. These many-core architectures bring up new capabilities, opportunities, as well as challenges. As the number of cores increases, so does the probability to have faults, both due to hardware issues (e.g., physical defects introduced during fabrication), software problems (e.g., a single crashed process bringing down the whole computation) or communication issues in the network infrastructure.

This workshop focuses on software and/or hardware solutions to dependability and fault-tolerance in multi- and many-core systems.

The DMCC Workshop topics of interest include (but are not limited to) the following:

  • Dependable/Fault-Tolerant Many-Core Architectures
  • Power-Aware Many-Core Design
  • Dependable & Secure Many-Core Designs
  • Many-Core Development and Design Tools
  • Dependability and Fault Tolerance in Simulation
  • System-Level Many-Core Implementation
  • Many-Core Interconnect Technology
  • Many-Core System-On-Chip Development
  • Reconfigurable Computing and FPGAs
  • Design for Testing
  • Hardware and Software Debug Facilities
  • Many-Core Programming and Optimization for Dependability
  • Application Partitioning and Load Balancing
  • Hypervisors and Virtual Machine Technology
  • Trusted and Untrusted Environments
  • Virtualization for Dependability
  • Dependability through Multi-Threading / Multi-Processing
  • Fault Detection Techniques
  • Fault-Tolerant Software Design
  • Fault-Tolerant Hardware Design
  • Fault-Tolerant HW/SW Co-Design
  • Modeling and Simulation of Dependable and Fault Tolerant Systems
  • Formal Techniques for Dependable Hardware/Software Design

IMPORTANT DATES

  • Paper Submissions: ------------------------------------ March 07, 2016
  • Acceptance Notification: ---------------------------------- April 07, 2016
  • Camera Ready Papers and Registration Due by: ------- May 01, 2016
  • Conference Dates: ---------------------------------------- July 18 - 22, 2016

WORKSHOP ORGANIZERS

  • Diana Gohringer - Ruhr-University Bochum (RUB), Germany
    Email: diana.goehringer@ruhr-uni-bochum.de
  • Thomas Hollstein - Tallinn University of Technology (TUT), Estonia
    Email: thomas@ati.ttu.ee

International Program Committee:

All submitted papers will be rigorously reviewed by the workshop technical program committee members following similar criteria used in HPCS 2016 and will be published as part of the HPCS 2016 Proceedings.

  • Juergen Becker, Karlsruhe Institute of Technology, Germany
  • Masoud Daneshtalab, KTH Royal Institute of Technology, Sweden
  • Masoumeh Ebrahimi, KTH Royal Institute of Technology, Sweden
  • Michael Huebner, Ruhr-University Bochum, Germany
  • Gert Jervan, Tallinn University of Technology, Estonia
  • Fernando Moraes, Pontificia Universidade Catolica do Rio Grande do Sul (PUCRS), Porto Alegre, Brazil
  • Maurizio Palesi, Kore University, Italy
  • Juha Plosila, University of Turku, Finland
  • Gerard Rauwerda, Recore Systems, The Netherlands
  • Mario Scholzel, IHP GmbH, Germany
  • Sascha Uhrig, Airbus Defense and Space GmbH, Germany
  • Theo Vierhaus, TU Cottbus, Germany
  • TBA, TBA

(* Committee formation is pending and will be finalized shortly.)

Event Details
Location: 
The University of Innsbruck, Austria
URL: 
http://hpcs2016.cisedu.info