PULPino: FREE and OPEN-SOURCE RISC-V microprocessor system

We are happy to share our FREE and OPEN-SOURCE microprocessor system PULPino!

You can download the entire source code, test programs, programming environment and even the bitstream for the popular ZEDboard, completely for free under the Solderpad license.

What you will get is a competitive, state-of-the-art 32-bit processor based on the RISC-V architecture, with a rich set of peripherals, and full debug support. At ETH Zurich and Universita' di Bologna we have put many of the ideas that we have developed on our research on ultra-low-power parallel processing (PULP project) into PULPino. It is the little hip brother to its more serious bigger brothers.

Are you excited about it? Stop reading right now, and go to:
https://github.com/pulp-platform/pulpino to download PULPino.

If you are not convinced easily, let us tell you more about the details:

The core: PULPino is an open-source microcontroller system, based on an optimized 32-bit RISC-V core developed at ETH Zurich and Universita' di Bologna. The core has an IPC close to 1, full support for the base integer instruction set (RV32I), compressed instructions (RV32C) and partial support for the multiplication instruction set extension (RV32M). It implements several ISA extensions such as: hardware loops, post-incrementing load and store instructions, ALU and MAC operations, which increase the efficiency of the core in low-power signal processing applications.

Peripherals: For communication with the outside world, PULPino contains a broad set of peripherals, including I2S, I2C, SPI and UART. The platform internal devices can be accessed from outside via JTAG and SPI which allows pre-loading RAMs with executable code. In standalone mode, the platform boots from an internal boot ROM and loads its program from an external SPI flash.

More features: To allow embedded operating systems such as FreeRTOS to run, a subset of the privileged specification is supported. When the core is idle, the platform can be put into a low power mode, where only a simple event unit is active and everything else is clock-gated and consumes minimal power (leakage). A specialized event unit wakes up the core in case an event/interrupt arrives.

Not a toy design: PULPino is a mature design: it has been taped-out as an ASIC in UMC 65nm in January 2016. The PULPino platform is available for RTL simulation as well for FPGA mapping. It has full debug support on all targets. In addition we support extended profiling with source code annotated execution times through KCacheGrind in RTL simulations.

And it is free, no registration, no strings attached, you can use it, change it, adapt it, add to your own chip, use it for classes, research, projects, products... We just ask you to acknowledge the source, and if possible, let us know what you like and what you like and don't like.

OPEN HARDWARE, THE WAY IT SHOULD BE!

The PULPino source code is available on github, see https://github.com/pulp-platform/pulpino
For more information on PULPino and PULP see our websites:
http://pulp.ethz.ch and http://www-micrel.deis.unibo.it/pulp-project/