Visible to the public Biblio

Filters: Author is Y. Yang  [Clear All Filters]
2018-05-16
Y. Jiang, Y. Yang, H. Liu, H. Kong, M. Gu, J. Sun, L. Sha.  2016.  From Stateflow Simulation to Verified Implementation: A Verification Approach and A Real-Time Train Controller Design. 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). :1-11.