PATMOS 2017
27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
25 - 27 September 2017 | Thessaloniki, Greece | http://patmos2017.web.auth.gr
PATMOS is Technically Sponsored by IEEE CASS. The conference proceedings will be included in the IEEE Xplore Digital Library.
The PATMOS 2017 objective is to provide a forum to discuss and investigate emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program will focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization. At the same time, power-efficiency has become extremely important for many more areas spreading far beyond this traditional R&D niche. Energy-efficient ICT (Information and Communication Technology) infrastructures are also a hot-topic that will be specially considered.
VARI 2017 is the 8th European Workshop on CMOS Variability. The increasing variability in CMOS transistor characteristics, as well as its sensitivity to environmental variations has become a major challenge to scaling and integration. This leads to major changes in the way that future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and device technology. VARI meeting answers to the need to have a European event on variability in CMOS circuits and technologies, where industry and academia meet to discuss and investigate the CMOS process and environmental variability issues in methodologies and tools for the design of current and upcoming generations of integrated circuits and systems. The technical program will focus on performance and power consumption as well as architectural aspects like adaptability or resilience, with particular emphasis on modeling, design, characterization, analysis and optimization of variability. Digital, Analog, Mixed Signal and RF circuits are within VARI scope. This year VARI will be a Special Session in PATMOS.
PATMOS and VARI take place in Thessaloniki, Greece. Thessaloniki sits in north Greece in a city which never doubted its own cultural identity and its millennia of existence, it stands there since 315BC. Historically one of Europe's oldest and most multiethnic cities, Thessaloniki is home to architectural marvels that testify to its centrality in Byzantine, Ottoman and Sephardic Jewish history. The city is anchored by Aristotelous Square, where curved, columned facades open to the waterfront in one direction and frame views of the historic Ano Poli (Upper City) in the other. Though it has only about one million people, compared with Athens' five million, Salonika is widely considered the cultural capital of Greece. Thessaloniki is truly unique in the sense that it intricately marries its thousands-year-old multicultural heritage with cutting-edge art performances and cinematic avant-garde.
Topics of Interest
Timing and Performance
- Methodologies and tools for the analysis, design and verification of timing and performance properties of integrated circuits and systems at all levels of abstraction;
- Design for yield, design for manufacturability;
- Simulation tools;
- Design and issues concerning asynchronous systems;
- Special timing or performance related topics, e.g. synchronization, side-channel attacks.
- Coupling efffects: analysis, modelling, simulation & experimentation
Low Power and Thermal-aware Design
- Design techniques for thermal-aware and low power circuits and systems
- Power/thermal-aware synthesis and floorplanning
- Policies for power and thermal optimization
- Power/Thermal Estimation and Optimization
- Power/Thermal-aware architectures
- Hardware-software interaction for power/temperature minimization
- Energy-harvesting
- Low Power Systems: wireless sensor networks, mobile computing
Compilers, operating systems and runtime systems
- Power efficiency through parallelizing compilers or parallel programming
- Concepts for programming novel multi-core architectures
- Real-time system compilers, operating systems and run-time systems
FPGAs and GPU-based accelerators
- Novel accelerator-based architectures and architectural features
- High-Level Abstractions and CAD tools for using accelerators
- Neuro-Inspired Accelerators for Computing
- Customized processor instruction sets
- Compilers optimizing for dynamically reconfigurable processor arrays (DRPAs)
- Case studies and challenges on DRPAs and accelerators
Power-efficient High-performance ICT and Data Centers
- Supercomputing: compilers, operating systems, run time systems
- Hardware-software interaction for low power high-performance
- Modeling and analysis of energy costs for ICT subsystems and infrastructures
- Power analysis for data centers, supercomputers, communication networks
- Cross layer approaches and new paradigms for power efficiency in ICT
- Power-efficient I/O interfaces and NoC design
- Low power high performance in extreme scale supercomputing
- Heterogeneous HPC by new storage technologies
- Case studies: test cases, or design study challenges on data stations or supercomputers
Application-specific power efficiency by algorithmic and analytic efforts
- Application of Computational Intelligence to implement high-performance systems (Neural Networks, Suport Vector Machines, Self-Organizing Maps, Neuromorphic systems)
- Banking, financial modeling and financial database acceleration
- Social networks, games, entertainment, ambient intelligence, ubiquitous and wearable computing
- Bioinformatics, bio-inspired, medical, and genetics systems and life sciences
- Physics and astronomy, weather prediction, oil and gas exploration.
- Security systems, cryptography, object recognition and tracking, global navigation satellite systems
- Audio/video, imaging, smart cameras, PDAs, smart image sensors, Reconfigurable Video Coding (RVC), etc. Aerospace, avionics, automotive and railway, and many other application areas
Design for aging
- Aging effects and their impact on circuits
- Aging-aware models
- Aging-aware timing and power analysis
- Circuit aging prediction
- Aging-aware design
Case studies
- Wireless health, green computing, ultra low-power embedded systems, displays
- Examples, studies or challenges presenting innovative solutions for thermal and power efficiency
- Studies and experiences in using Azido
- Studies on energy efficiency by paradigm shift, by heterogeneous solutions or new storage technologies
- Case Studies on power efficiency of data stations
- Security systems, cryptography, object recognition and tracking, global navigation satellite systems
- Audio/video, imaging, smart cameras, PDAs, smart image sensors, Reconfigurable Video Coding (RVC), etc. Aerospace, avionics, automotive and railway, and many other application areas