PULP Platform: New, Free Open-Source Risc-V cores available for download
It is our pleasure to announce a major release of our open source (Hardware and Software) Risc-V based PULP platform!
We have just released an update for our PULPino system available from
https://github.com/pulp-platform/pulpino
We now have two different cores,
- RI5CY: 4-stage pipeline with our custom DSP extensions
- Zero-riscy: 2-stage pipeline, optimized for a smaller area.
Each of these two cores has configuration options leading to four different major configurations, for which we also release bit-files for the Xilinx ZedBoard
- RI5CY: This is the core that was available until now, with updates and fixes RI5CY + FPU: There is now a 32bit FPU (fully compliant to the RISC-V ISA) available to be used with RI5CY
- Zero-Riscy: The small-area core, implementing the standard RV32-ICM, no DSP extensions
- Micro-Riscy: For even smaller area, implements the (E) extension with only 16 registers and has no hardware multiplier
There are also various updates to the RI5CY core and peripherals, thanks to everyone for reporting problems.
We are currently working on PULPino v2, which will continue to use these cores, but will have a slightly different overall architecture to reduce regular I/O to memory transfers.
This version will also come with its virtual platform, so stay tuned.
More info, docs and technical details on IPC, area and speed achievable on the newly released cores can be found here
http://pulp-platform.org
The PULP team