Visible to the public Biblio

Filters: Author is Kong, Shuyu  [Clear All Filters]
2020-04-06
Shen, Yuanqi, Li, You, Kong, Shuyu, Rezaei, Amin, Zhou, Hai.  2019.  SigAttack: New High-level SAT-based Attack on Logic Encryptions. 2019 Design, Automation Test in Europe Conference Exhibition (DATE). :940–943.
Logic encryption is a powerful hardware protection technique that uses extra key inputs to lock a circuit from piracy or unauthorized use. The recent discovery of the SAT-based attack with Distinguishing Input Pattern (DIP) generation has rendered all traditional logic encryptions vulnerable, and thus the creation of new encryption methods. However, a critical question for any new encryption method is whether security against the DIP-generation attack means security against all other attacks. In this paper, a new high-level SAT-based attack called SigAttack has been discovered and thoroughly investigated. It is based on extracting a key-revealing signature in the encryption. A majority of all known SAT-resilient encryptions are shown to be vulnerable to SigAttack. By formulating the condition under which SigAttack is effective, the paper also provides guidance for the future logic encryption design.
2018-02-27
Kong, Shuyu, Shen, Yuanqi, Zhou, Hai.  2017.  Using Security Invariant To Verify Confidentiality in Hardware Design. Proceedings of the on Great Lakes Symposium on VLSI 2017. :487–490.

Due to the increasing complexity of design process, outsourcing, and use of third-party blocks, it becomes harder and harder to prevent Trojan insertion and other malicious design modifications. In this paper, we propose to deploy security invariant as carried proof to prevent and detect Trojans and malicious attacks and to ensure the security of hardware design. Non-interference with down-grading policy is checked for confidentiality. Contrary to existing approaches by type checking, we develop a method to model-check a simple safety property on a composed machine. Down-grading is handled in a better way in model-checking and the effectiveness of our approach is demonstrated on various Verilog benchmarks.