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Filters: Author is Ho, W.-G.  [Clear All Filters]
2021-03-09
Ho, W.-G., Ng, C.-S., Kyaw, N. A., Lwin, N. Kyaw Zwa, Chong, K.-S., Gwee, B.-H..  2020.  High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC. 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). :161—164.

We propose a high efficiency Early-Complete Brute Force Elimination method that speeds up the analysis flow of the Camouflage Integrated Circuit (IC). The proposed method is targeted for security qualification of the Camouflaged IC netlists in Intellectual Property (IP) protection. There are two main features in the proposed method. First, the proposed method features immediate elimination of the incorrect Camouflage gates combination for the rest of computation, concentrating the resources into other potential correct Camouflage gates combination. Second, the proposed method features early complete, i.e. revealing the correct Camouflage gates once all incorrect gates combination are eliminated, increasing the computation speed for the overall security analysis. Based on the Python programming platform, we implement the algorithm of the proposed method and test it for three circuits including ISCAS’89 benchmarks. From the simulation results, our proposed method, on average, features 71% lesser number of trials and 79% shorter run time as compared to the conventional method in revealing the correct Camouflage gates from the Camouflaged IC netlist.