Visible to the public Biblio

Filters: Author is Makris, Yiorgos  [Clear All Filters]
2018-01-23
Yasin, Muhammad, Sengupta, Abhrajit, Schafer, Benjamin Carrion, Makris, Yiorgos, Sinanoglu, Ozgur, Rajendran, Jeyavijayan(JV).  2017.  What to Lock?: Functional and Parametric Locking Proceedings of the on Great Lakes Symposium on VLSI 2017. :351–356.

Logic locking is an intellectual property (IP) protection technique that prevents IP piracy, reverse engineering and overbuilding attacks by the untrusted foundry or end-users. Existing logic locking techniques are all based on locking the functionality; the design/chip is nonfunctional unless the secret key has been loaded. Existing techniques are vulnerable to various attacks, such as sensitization, key-pruning, and signal skew analysis enabled removal attacks. In this paper, we propose a tenacious and traceless logic locking technique, TTlock, that locks functionality and provably withstands all known attacks, such as SAT-based, sensitization, removal, etc. TTLock protects a secret input pattern; the output of a logic cone is flipped for that pattern, where this flip is restored only when the correct key is applied. Experimental results confirm our theoretical expectations that the computational complexity of attacks launched on TTLock grows exponentially with increasing key-size, while the area, power, and delay overhead increases only linearly. In this paper, we also coin ``parametric locking," where the design/chip behaves as per its specifications (performance, power, reliability, etc.) only with the secret key in place, and an incorrect key downgrades its parametric characteristics. We discuss objectives and challenges in parametric locking.

2017-04-20
Ahmadi, Ali, Bidmeshki, Mohammad-Mahdi, Nahar, Amit, Orr, Bob, Pas, Michael, Makris, Yiorgos.  2016.  A Machine Learning Approach to Fab-of-origin Attestation. Proceedings of the 35th International Conference on Computer-Aided Design. :92:1–92:6.

We introduce a machine learning approach for distinguishing between integrated circuits fabricated in a ratified facility and circuits originating from an unknown or undesired source based on parametric measurements. Unlike earlier approaches, which seek to achieve the same objective in a general, design-independent manner, the proposed method leverages the interaction between the idiosyncrasies of the fabrication facility and a specific design, in order to create a customized fab-of-origin membership test for the circuit in question. Effectiveness of the proposed method is demonstrated using two large industrial datasets from a 65nm Texas Instruments RF transceiver manufactured in two different fabrication facilities.