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2022-03-08
Kazemi, Arman, Sharifi, Mohammad Mehdi, Laguna, Ann Franchesca, Müller, Franz, Rajaei, Ramin, Olivo, Ricardo, Kämpfe, Thomas, Niemier, Michael, Hu, X. Sharon.  2021.  In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories. 2021 Design, Automation Test in Europe Conference Exhibition (DATE). :1084—1089.
Nearest neighbor (NN) search is an essential operation in many applications, such as one/few-shot learning and image classification. As such, fast and low-energy hardware support for accurate NN search is highly desirable. Ternary content-addressable memories (TCAMs) have been proposed to accelerate NN search for few-shot learning tasks by implementing \$L\$∞ and Hamming distance metrics, but they cannot achieve software-comparable accuracies. This paper proposes a novel distance function that can be natively evaluated with multi-bit content-addressable memories (MCAMs) based on ferroelectric FETs (Fe-FETs) to perform a single-step, in-memory NN search. Moreover, this approach achieves accuracies comparable to floating-point precision implementations in software for NN classification and one/few-shot learning tasks. As an example, the proposed method achieves a 98.34% accuracy for a 5-way, 5-shot classification task for the Omniglot dataset (only 0.8% lower than software-based implementations) with a 3-bit MCAM. This represents a 13% accuracy improvement over state-of-the-art TCAM-based implementations at iso-energy and iso-delay. The presented distance function is resilient to the effects of FeFET device-to-device variations. Furthermore, this work experimentally demonstrates a 2-bit implementation of FeFET MCAM using AND arrays from GLOBALFOUNDRIES to further validate proof of concept.
2017-08-18
Bi, Yu, Hu, X. Sharon, Jin, Yier, Niemier, Michael, Shamsi, Kaveh, Yin, Xunzhao.  2016.  Enhancing Hardware Security with Emerging Transistor Technologies. Proceedings of the 26th Edition on Great Lakes Symposium on VLSI. :305–310.

We consider how the I-V characteristics of emerging transistors (particularly those sponsored by STARnet) might be employed to enhance hardware security. An emphasis of this work is to move beyond hardware implementations of physically unclonable functions (PUFs) and random num- ber generators (RNGs). We highlight how new devices (i) may enable more sophisticated logic obfuscation for IP protection, (ii) could help to prevent fault injection attacks, (iii) prevent differential power analysis in lightweight cryptographic systems, etc.