Visible to the public Biblio

Filters: Keyword is Compaction  [Clear All Filters]
2022-03-14
Narang, Anuraag, Venu, Balaji, Khursheed, Saqib, Harrod, Peter.  2021.  An Exploration of Microprocessor Self-Test Optimisation Based On Safe Faults. 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT). :1—6.
Microprocessor software test libraries (STLs) must provide maximum fault coverage with minimum overhead. Pruning safe faults, which cannot cause errors in the output of the processor, from the fault list can increase fault coverage without adding test overhead. Applying more application-specific constraints can lead to the identification of more safe faults, and some such constraints are yet to be explored. This work explores the use of signal combination-based constraints alongside well-known constant signal-based constraints for identifying safe faults. Also, for the first time, information on safe faults is utilised during test compaction in order to further minimise test overhead. Results for an OpenRISC processor design show up to 2.33% improvement in fault coverage with the use of the proposed constraints. In one test program, a code segment contributing only to the coverage of safe faults is identified, with its removal providing a 1.09 % code size reduction on top of existing compaction techniques. The results may vary for a larger and more complex commercial design with greater scope for redundant logic. This work explores the use of signal combination-based constraints alongside well-known constant signal-based constraints for identifying safe faults. Also, for the first time, information on safe faults is utilised during test compaction in order to further minimise test overhead. Results for an OpenRISC processor design show up to 2.33% improvement in fault coverage with the use of the proposed constraints. In one test program, a code segment contributing only to the coverage of safe faults is identified, with its removal providing a 1.09 % code size reduction on top of existing compaction techniques. The results may vary for a larger and more complex commercial design with greater scope for redundant logic.
2022-02-04
Septiani, Ardita, Ikaningsih, Manty A., Sari, Tanti P., Idayanti, Novrita, Dedi.  2021.  The Behaviour of Magnetic Properties and Electromagnetic Absorption of MgFe2O4 prepared by Powder Metallurgy Method. 2021 International Conference on Radar, Antenna, Microwave, Electronics, and Telecommunications (ICRAMET). :136–140.
This study focuses on the behavior of magnetic properties and electromagnetic absorption of MgFe2O4 prepared by powder metallurgy. Magnesium ferrite was synthesized using oxide precursors (MgO and Fe2 O3). The samples were calcined at 700 °C for 3 hours and sintered at 1100 °C for 24 hours with varying compaction pressure (80 kg/cm2, 90 kg/cm2, 100 kg/cm2). Magnesium ferrites were characterized using an X-Ray Diffraction (XRD) for their crystal structure analysis, a Scanning Electron Microscope equipped with an Energy Dispersive Spectroscopy (SEM-EDS) for their microstructure and elemental composition studies, a Permagraph for their magnetic properties, and a Vector Network Analysis (VNA) for their microwave absorption characteristics. XRD patterns shows primary phase of MgFe2O4 and secondary phase of Fe2 O3 present in all three samples. The SEM characterization reveal the microstructure of magnesium ferrite and the EDS spectra confirm the presence of Fe, Mg, and O. The hysteresis curves show that the values of remanence magnetic induction (Br) are 17.5 emu/g, 16.5 emu/g, and 14.5 emu/g, respective to the increasing compaction pressure. Saturation magnetization values are increasing whereas the coercivity values are found to have inconsistent change with increasing compaction pressure. According to VNA results, the values of reflection loss are -16.15 dB, -22.45 dB, and -27.55 dB, respectively.
2015-05-06
Cook, A., Wunderlich, H.-J..  2014.  Diagnosis of multiple faults with highly compacted test responses. Test Symposium (ETS), 2014 19th IEEE European. :1-6.

Defects cluster, and the probability of a multiple fault is significantly higher than just the product of the single fault probabilities. While this observation is beneficial for high yield, it complicates fault diagnosis. Multiple faults will occur especially often during process learning, yield ramp-up and field return analysis. In this paper, a logic diagnosis algorithm is presented which is robust against multiple faults and which is able to diagnose multiple faults with high accuracy even on compressed test responses as they are produced in embedded test and built-in self-test. The developed solution takes advantage of the linear properties of a MISR compactor to identify a set of faults likely to produce the observed faulty signatures. Experimental results show an improvement in accuracy of up to 22 % over traditional logic diagnosis solutions suitable for comparable compaction ratios.