Biblio

This work demonstrates an ultra-compact low power oscillating micromechanical active pixel array based on a 0.35 μm back-end of line (BEOL)-embedded CMOS-MEMS technology. Each pixel consists of a 3-MHz clamped-clamped beam (CCB) MEMS resonator and a power scalable transimpedance amplifier (TIA) that occupies a small area of 70 × 60 μm2 and draws only 85 μW/pixel. The MEMS resonator is placed next to the TIA with less than 10 μm spacing thanks to the well-defined etch stops in the titanium nitride composite (TiN-C) CMOS-MEMS platform. A multiplexing phase-locked loop (PLL)-driven oscillator is employed to demonstrate the chip functionality. In particular, a nonlinear operation of the resonator tank is used to optimize the phase noise (PN) performance and Allan deviation (ADEV) behavior. The ADEV of 420 ppb averaged over best 3-pixels is exhibited based on such a nonlinear vibration operation.

Double differential phase shift keying(DDPSK) modulation is an efficient method to compensate the Doppler shifts, whereas the phase noise will be amplified which results in the signal-to-noise ratio (SNR) loss. In this paper, we propose a novel receiver architecture for underwater acoustic DSSS communications with Doppler shifts. The proposed method adopts not only the DDPSK modulation to compensate the Doppler shifts, but also the improved bit-interleaved coded modulation with iterative decoding (BICM-ID) algorithm for DDPSK to recover the SNR loss. The improved DDPSK demodulator adopts the multi-symbol estimation to track the channel variation, and an extended trellis diagram is constructed for DDPSK demodulator. Theoretical simulation shows that our system can obtain around 10.2 dB gain over the uncoded performance, and 7.4 dB gain over the hard-decision decoding performance. Besides, the experiment conducted in the Songhua Lake also shows that the proposed receiver can achieve lower BER performance when Doppler shifts exists.

An experiment and numerical simulations analyze low-speed OSC derived XPM-induced phase noise penalty in 100-Gbps WDM systems. WDM transmission performance exhibits signal bit-pattern dependence on OSC, which is due to deterioration in SD-FEC performance.

Clock and data recovery (CDR) systems are the first logic blocks in serial data receivers and the latter's performance depends on the CDR. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe is presented. The CDR uses an injection locked oscillator (ILO) which delivers the 100 GHz clock. The inherent phase shift between the recovered clock and the incoming data is compensated by a feedback loop which performs phase and frequency tracking. Furthermore, a windowed phase comparator has been used, first to lower the classical number of gates, in order to prevent any delay skews between the different phase detector blocks, then to decrease the phase comparator operating frequency, and furthermore to extend the ability to track zero bit patterns The measurements results demonstrate a 100 GHz clock signal extracted from 50 Gb/s input data, with a phase noise as low as 98 dBc/Hz at 100 kHz offset from the carrier frequency. The rms jitter of the 25 GHz recovered data is only 1.2 ps. The power consumption is 1.4 W under 2.3 V power supply.