Visible to the public Biblio

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2022-07-29
Mishchenko, Mikhail A., Bolshakov, Denis I., Matrosov, Valery V., Sysoev, Ilya V..  2021.  Electronic neuron-like generator with excitable and self-oscillating behavior. 2021 5th Scientific School Dynamics of Complex Networks and their Applications (DCNA). :1–2.
Experimental implementation of phase-locked loop (PLL) with bandpass filter is proposed. Such PLL is noteworthy for neuron-like dynamics. It generates both regular and chaotic spikes and bursts. Previously proposed hardware implementation of this system has significant disadvantage – absence of excitable (non-oscillating) mode that is vital for brain neurons. The proposed electronic neuron-like generator is modified and could be used for hardware implementation of spiking neural networks.
2020-03-27
Richter, Michael, Mehlmann, Gert, Luther, Matthias.  2019.  Grid Code Compliant Modeling and Control of Modular Multilevel Converters during Unbalanced Faults. 2019 54th International Universities Power Engineering Conference (UPEC). :1–6.

This paper presents necessary modeling and control enhancements for Modular Multilevel Converters (MMC) to provide Fault-Ride-Through capability and fast fault current injection as required by the new German Technical Connection Rules for HVDC. HVDC converters have to be able to detect and control the grid voltage and grid currents accurately during all fault conditions. That applies to the positive as well as negative sequence components, hence a Decoupled Double Synchronous Reference Frame - Phase-Locked-Loop (DDSRF-PLL) and Current Control (DDSRF-CC) are implemented. In addition, an enhanced current limitation and an extension of the horizontal balancing control are proposed to complement the control structure for safe operation.

2015-05-06
Béraud-Sudreau, Q., Begueret, J.-B., Mazouffre, O., Pignol, M., Baguena, L., Neveu, C., Deval, Y., Taris, T..  2014.  SiGe Clock and Data Recovery System Based on Injection-Locked Oscillator for 100 Gbit/s Serial Data Link. Solid-State Circuits, IEEE Journal of. 49:1895-1904.

Clock and data recovery (CDR) systems are the first logic blocks in serial data receivers and the latter's performance depends on the CDR. In this paper, a 100 Gbit/s CDR designed in 130 nm BiCMOS SiGe is presented. The CDR uses an injection locked oscillator (ILO) which delivers the 100 GHz clock. The inherent phase shift between the recovered clock and the incoming data is compensated by a feedback loop which performs phase and frequency tracking. Furthermore, a windowed phase comparator has been used, first to lower the classical number of gates, in order to prevent any delay skews between the different phase detector blocks, then to decrease the phase comparator operating frequency, and furthermore to extend the ability to track zero bit patterns The measurements results demonstrate a 100 GHz clock signal extracted from 50 Gb/s input data, with a phase noise as low as 98 dBc/Hz at 100 kHz offset from the carrier frequency. The rms jitter of the 25 GHz recovered data is only 1.2 ps. The power consumption is 1.4 W under 2.3 V power supply.