Biblio

Differential Power Analysis (DPA) attacks were shown to be effective in recovering the secret key information from a variety cryptographic systems. In response, several design methods, ranging from the cell level to the algorithmic level, have been proposed to defend against DPA attacks. Cell level solutions depend on DPA resistant cell designs which attempt to minimize power variance during transitions while minimizing area and power consumption. In this paper, we discuss how a differential circuit design style is incorporated into a COTS tool set, resulting in a fully automated synthesis system DPA resistant integrated circuits. Based on the Secure Differential Multiplexer Logic (SDMLp), this system can be used to synthesize complete cryptographic processors which provide strong defense against DPA while minimizing area and power overhead. We discuss how both combinational and sequential cells are incorporated in the cell library. We show the effectiveness of the tool chain by using it to automatically synthesize the layouts, from RT level Verilog specifications, of both the DES and AES encryption ICs in 90nm CMOS. In each case, we present experimental data to demonstrate DPA attack resistance and area, power and performance overhead and compare these with circuits synthesized in another differential logic called MDPL as well as standard CMOS synthesis results.

In this paper, We propose DNA sticker model based algorithm, a computability model, which is a simulation of the parallel computations using the Molecular computing as in Adelman's DNA computing experiment, it demonstrates how to use a sticker-based model to design a simple DNA-based algorithm for attacking a linear and a non-linear feedback shift register (FSR) based stream cipher. The algorithm first construct the TEST TUBE contains all overall solution space of memory complexes for the cipher and initials of registers via the sticker-based model. Then, with biological operations, separate and combine, we remove those which encode illegal plain and key stream from the TEST TUBE of memory complexes, the decision based on verifying a key stream bit this bit represented by output of LFSRs equation. The model anticipates two basic groups of single stranded DNA molecules in its representation one of a genetic bases and second of a bit string, It invests parallel search into the space of solutions through the possibilities of DNA computing and makes use of the method of cryptanalysis of algebraic code as a decision technique to accept the solution or not, and their operations are repeated until one solution or limited group of solutions is reached. The main advantages of the suggested algorithm are limited number of cipher characters, and finding one exact solution The present work concentrates on showing the applicability of DNA computing concepts as a powerful tool in breaking cryptographic systems.

Elliptic curve asymmetric cryptography has achieved increased popularity due to its capability of providing comparable levels of security as other existing cryptographic systems while requiring less computational work. Pollard Rho and Parallel Collision Search, the fastest known sequential and parallel algorithms for breaking this cryptographic system, have been successfully applied over time to break ever-increasing bit-length system instances using implementations heavily optimized for the available hardware. This work presents portable, general implementations of a Parallel Collision Search based solution for prime elliptic curve asymmetric cryptographic systems that use publicly available big integer libraries and make no assumption on prime curve properties. It investigates which bit-length keys can be broken in reasonable time by a user that has access to a state of the art, public HPC equipment with CPUs and GPUs. The final implementation breaks a 79-bit system in about two hours using 80 GPUs and 94-bits system in about 15 hours using 256 GPUs. Extensive experimentation investigates scalability of CPU, GPU and CPU+GPU runs. The discussed results indicate that speed-up is not a good metric for parallel scalability. This paper proposes and evaluates a new metric that is better suited for this task.