| Title | Automated Synthesis of Differential Power Attack Resistant Integrated Circuits |
| Publication Type | Conference Paper |
| Year of Publication | 2019 |
| Authors | Gohil, Nikhil N., Vemuri, Ranga R. |
| Conference Name | 2019 IEEE National Aerospace and Electronics Conference (NAECON) |
| Keywords | Automated Response Actions, Automated Synthesis, CMOS logic circuits, CMOS synthesis, combinational cells, combinational circuits, composability, cryptographic processors, cryptographic systems, cryptography, differential circuit design, differential logic, Differential Power Analysis, differential power analysis attacks, differential power attack resistant integrated circuits, DPA attack resistance, DPA resistant cell designs, Dynamic Differential Logic, fully automated synthesis system DPA resistant integrated circuits, hardware security, Libraries, logic design, Logic gates, MDPL, multiplying circuits, power consumption, Power demand, private key cryptography, pubcrawl, Resiliency, Resistance, RT level Verilog specifications, secret key information, Secure Differential Multiplexer Logic, sequential cells, sequential circuits, Standards, Tools |
| Abstract | Differential Power Analysis (DPA) attacks were shown to be effective in recovering the secret key information from a variety cryptographic systems. In response, several design methods, ranging from the cell level to the algorithmic level, have been proposed to defend against DPA attacks. Cell level solutions depend on DPA resistant cell designs which attempt to minimize power variance during transitions while minimizing area and power consumption. In this paper, we discuss how a differential circuit design style is incorporated into a COTS tool set, resulting in a fully automated synthesis system DPA resistant integrated circuits. Based on the Secure Differential Multiplexer Logic (SDMLp), this system can be used to synthesize complete cryptographic processors which provide strong defense against DPA while minimizing area and power overhead. We discuss how both combinational and sequential cells are incorporated in the cell library. We show the effectiveness of the tool chain by using it to automatically synthesize the layouts, from RT level Verilog specifications, of both the DES and AES encryption ICs in 90nm CMOS. In each case, we present experimental data to demonstrate DPA attack resistance and area, power and performance overhead and compare these with circuits synthesized in another differential logic called MDPL as well as standard CMOS synthesis results. |
| DOI | 10.1109/NAECON46414.2019.9057882 |
| Citation Key | gohil_automated_2019 |
Automated Synthesis of Differential Power Attack Resistant Integrated Circuits