Biblio

Dynamic Random Access Memory (DRAM) is widely used for data storage and, when a computer system is in operation, the DRAM can contain sensitive information such as passwords and cryptographic keys. Therefore, the DRAM is a prime target for hardware-based cryptanalytic attacks. These attacks can be performed in the supply chain to capture default key mechanisms enabling a later cyber attack or predisposition the system to remote effects. Two prominent attack classes against memory are the Cold Boot attack which recovers the data from the DRAM even after a supposed power-down and Rowhammer attack which violates memory integrity by influencing the stored bits to flip. In this paper, we propose an on-chip technique that obfuscates the memory addresses and data and provides a fast detect-response to defend against these hardware-based security attacks on DRAM. We advance the prior hardware security research by making two contributions. First, the key material is detected and erased before the Cold Boot attacker can extract the memory data. Second, our solution is on-chip and does not require nor depend on additional hardware or software which are open to additional supply chain attack vectors. We analyze the efficacy of our scheme through circuit simulation and compare the results to the previous mitigation approaches based on DRAM write operations. Our simulation and analysis results show that purging key information used for address and data randomization can be achieved much faster and with lower power than with typical DRAM write techniques used for sanitizing memory content. We demonstrate through circuit simulation of the key register design a technique that clears key information within 2.4ns which is faster by more than two orders magnitude compared to typical DRAM write operations for 180nm technology, and with a power consumption of 0.15 picoWatts.

Generalized chaos systems have more complex dynamic behavior than conventional chaos systems. If a generalized response system can be synchronized with a conventional drive system, the flexible control parameters and unpredictable synchronization state will increase significantly. The study first constructs a four-dimensional nonlinear dynamic equation with quadratic variables as a drive system. The numerical simulation and analyses of the Lyapunov exponent show that it is also a chaotic system. Based on the generalized chaos synchronization (GCS) theory, a four-dimensional diffeomorphism function is designed, and the corresponding GCS response system is generated. Simultaneously, the structural and synchronous circuits of information interaction and control are constructed with Multisim™ software, with the circuit simulation resulting in a good agreement with the numerical calculations. In order to verify the practical effect of generalized synchronization, an RGB digital image secure communication scheme is proposed. We confuse a 24-bit true color image with the designed GCS system, extend the original image to 48-bits, analyze the scheme security from keyspace, key sensitivity and non-symmetric identity authentication, classical types of attacks, and statistical average from the histogram, image correlation. The research results show that this GCS system is simple and feasible, and the encryption algorithm is closely related to the confidential information, which can resist the differential attack. The scheme is suitable to be applied in network images or other multimedia safe communications.

A method for the multiple faults diagnosis in linear analog circuits is presented in this paper. The proposed approach is based upon the concept named by the indirect compensation theorem. This theorem is reducing the procedure of fault diagnosis in the analog circuit to the symbolic analysis process. An extension of the indirect compensation theorem for the linear subcircuit is proposed. The indirect compensation provides equivalent replacement of the n-ports subcircuit by n norators and n fixators of voltages and currents. The proposed multiple faults diagnosis techniques can be used for evaluation of any kind of terminal characteristics of the two-port network. For calculation of the circuit determinant expressions, the Generalized Parameter Extraction Method is implemented. The main advantage of the analysis method is that it is cancellation free. It requires neither matrix nor ordinary graph description of the circuit. The process of symbolic circuit analysis is automated by the freeware computer program Cirsym which can be used online. The experimental results are presented to show the efficiency and reliability of the proposed technique.