| Title | On-Chip Randomization for Memory Protection Against Hardware Supply Chain Attacks to DRAM |
| Publication Type | Conference Paper |
| Year of Publication | 2020 |
| Authors | Meadows, B., Edwards, N., Chang, S.-Y. |
| Conference Name | 2020 IEEE Security and Privacy Workshops (SPW) |
| Date Published | may |
| Keywords | circuit simulation, Cold Boot Attack, cryptography, DRAM, Hardware, Memory Protection, pubcrawl, Random access memory, resilience, Resiliency, Rowhammer attack, Scalability, Security by Default, Software, supply chain protection, Supply chains, system-on-chip |
| Abstract | Dynamic Random Access Memory (DRAM) is widely used for data storage and, when a computer system is in operation, the DRAM can contain sensitive information such as passwords and cryptographic keys. Therefore, the DRAM is a prime target for hardware-based cryptanalytic attacks. These attacks can be performed in the supply chain to capture default key mechanisms enabling a later cyber attack or predisposition the system to remote effects. Two prominent attack classes against memory are the Cold Boot attack which recovers the data from the DRAM even after a supposed power-down and Rowhammer attack which violates memory integrity by influencing the stored bits to flip. In this paper, we propose an on-chip technique that obfuscates the memory addresses and data and provides a fast detect-response to defend against these hardware-based security attacks on DRAM. We advance the prior hardware security research by making two contributions. First, the key material is detected and erased before the Cold Boot attacker can extract the memory data. Second, our solution is on-chip and does not require nor depend on additional hardware or software which are open to additional supply chain attack vectors. We analyze the efficacy of our scheme through circuit simulation and compare the results to the previous mitigation approaches based on DRAM write operations. Our simulation and analysis results show that purging key information used for address and data randomization can be achieved much faster and with lower power than with typical DRAM write techniques used for sanitizing memory content. We demonstrate through circuit simulation of the key register design a technique that clears key information within 2.4ns which is faster by more than two orders magnitude compared to typical DRAM write operations for 180nm technology, and with a power consumption of 0.15 picoWatts. |
| DOI | 10.1109/SPW50608.2020.00044 |
| Citation Key | meadows_-chip_2020 |
On-Chip Randomization for Memory Protection Against Hardware Supply Chain Attacks to DRAM