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2020-06-26
Putro, Singgih Nugroho, Moses Setiadi, De Rosal Ignatius, Aini, Devita Nurul, Rachmawanto, Eko Hari, Sari, Christy Atika.  2019.  Improved CRT Image Steganography based on Edge Areas and Spread Embedding. 2019 Fourth International Conference on Informatics and Computing (ICIC). :1—6.

Chinese Remainder Theorem (CRT) is one of the spatial domain methods that is more implemented in the data hiding method watermarking. CRT is used to improve security and imperceptibility in the watermarking method. CRT is rarely studied in studies that discuss steganographic images. Steganography research focuses more on increasing imperceptibility, embedded payload, and message security, so methods like LSB are still popular to be developed to date. CRT and LSB have some similarities such as default payload capacity and both are methods in the spatial domain which can produce good imperceptibility quality of stego image. But CRT is very superior in terms of security, so CRT is also widely used in cryptographic algorithms. Some ways to increase imperceptibility in image steganography are edge detection and spread spectrum embedding. This research proposes a combination of edge detection techniques and spread-spectrum embedding based on the CRT method to produce imperceptibility and safe image steganography method. Based on the test results it is proven that the combination of the proposed methods can increase imperceptibility of CRT-based steganography based on SSIM metric.

2018-02-21
Bai, Xu, Jiang, Lei, Dai, Qiong, Yang, Jiajia, Tan, Jianlong.  2017.  Acceleration of RSA processes based on hybrid ARM-FPGA cluster. 2017 IEEE Symposium on Computers and Communications (ISCC). :682–688.

Cooperation of software and hardware with hybrid architectures, such as Xilinx Zynq SoC combining ARM CPU and FPGA fabric, is a high-performance and low-power platform for accelerating RSA Algorithm. This paper adopts the none-subtraction Montgomery algorithm and the Chinese Remainder Theorem (CRT) to implement high-speed RSA processors, and deploys a 48-node cluster infrastructure based on Zynq SoC to achieve extremely high scalability and throughput of RSA computing. In this design, we use the ARM to implement node-to-node communication with the Message Passing Interface (MPI) while use the FPGA to handle complex calculation. Finally, the experimental results show that the overall performance is linear with the number of nodes. And the cluster achieves 6× 9× speedup against a multi-core desktop (Intel i7-3770) and comparable performance to a many-core server (288-core). In addition, we gain up to 2.5× energy efficiency compared to these two traditional platforms.