Acceleration of RSA processes based on hybrid ARM-FPGA cluster
| Title | Acceleration of RSA processes based on hybrid ARM-FPGA cluster |
| Publication Type | Conference Paper |
| Year of Publication | 2017 |
| Authors | Bai, Xu, Jiang, Lei, Dai, Qiong, Yang, Jiajia, Tan, Jianlong |
| Conference Name | 2017 IEEE Symposium on Computers and Communications (ISCC) |
| Date Published | jul |
| ISBN Number | 978-1-5386-1629-1 |
| Keywords | Acceleration, Algorithm design and analysis, ARM CPU, Chinese remainder theorem, cluster, cluster infrastructure, Clustering algorithms, Computer architecture, CRT, field programmable gate arrays, FPGA fabric, Hardware, Heterogeneous, hybrid architectures, hybrid ARM-FPGA cluster, Intel i7-3770, many-core server, message passing, message passing interface, Metrics, microprocessor chips, MPI, Multicore Computing, multicore computing security, multicore desktop, multiprocessing systems, node-to-node communication, none-subtraction Montgomery algorithm, Program processors, pubcrawl, public key cryptography, resilience, Resiliency, RSA, RSA algorithm, RSA processes acceleration, Scalability, software-hardware cooperation, system-on-chip, Xilinx Zynq SoC, Zynq |
| Abstract | Cooperation of software and hardware with hybrid architectures, such as Xilinx Zynq SoC combining ARM CPU and FPGA fabric, is a high-performance and low-power platform for accelerating RSA Algorithm. This paper adopts the none-subtraction Montgomery algorithm and the Chinese Remainder Theorem (CRT) to implement high-speed RSA processors, and deploys a 48-node cluster infrastructure based on Zynq SoC to achieve extremely high scalability and throughput of RSA computing. In this design, we use the ARM to implement node-to-node communication with the Message Passing Interface (MPI) while use the FPGA to handle complex calculation. Finally, the experimental results show that the overall performance is linear with the number of nodes. And the cluster achieves 6x 9x speedup against a multi-core desktop (Intel i7-3770) and comparable performance to a many-core server (288-core). In addition, we gain up to 2.5x energy efficiency compared to these two traditional platforms. |
| URL | http://ieeexplore.ieee.org/document/8024607/?reload=true |
| DOI | 10.1109/ISCC.2017.8024607 |
| Citation Key | bai_acceleration_2017 |
- resilience
- MPI
- Multicore Computing
- multicore computing security
- multicore desktop
- multiprocessing systems
- node-to-node communication
- none-subtraction Montgomery algorithm
- Program processors
- pubcrawl
- public key cryptography
- microprocessor chips
- Resiliency
- RSA
- RSA algorithm
- RSA processes acceleration
- Scalability
- software-hardware cooperation
- system-on-chip
- Xilinx Zynq SoC
- Zynq
- FPGA fabric
- Algorithm design and analysis
- ARM CPU
- Chinese remainder theorem
- cluster
- cluster infrastructure
- Clustering algorithms
- computer architecture
- CRT
- field programmable gate arrays
- Acceleration
- Hardware
- Heterogeneous
- hybrid architectures
- hybrid ARM-FPGA cluster
- Intel i7-3770
- many-core server
- message passing
- message passing interface
- Metrics