Biblio

True Random Number Generator (TRNG) is an important hardware security primitive for system security. TRNGs are capable of providing random bits for initialization vectors in encryption engines, for padding and nonces in authentication protocols and for seeds to pseudo random number generators (PRNG). A TRNG needs to meet the same statistical quality standards as a physical unclonable function (PUF) with regard to randomness and uniqueness, and therefore one can envision a unified architecture for both functions. In this paper, we investigate a FPGA implementation of a TRNG using the Shift-register Reconvergent-Fanout (SiRF) PUF. The SiRF PUF measures path delays as a source of entropy within a engineered logic gate netlist. The delays are measured at high precision using a time-to-digital converter, and then processed into a random bitstring using a series of linear-time mathematical operations. The SiRF PUF algorithm that is used for key generation is reused for the TRNG, with simplifications that improve the bit generation rate of the algorithm. This enables the TRNG to leverage both fixed PUF-based entropy and random noise sources, and makes the TRNG resilient to temperature-voltage attacks. TRNG bitstrings generated from a programmable logic implementation of the SiRF PUF-TRNG on a set of FPGAs are evaluated using statistical testing tools.

Present day's data security plays a vital role in digital human life. Data is a valuable asset to any organization and hence its security from external attacks is very important. Information security is not only an important aspect but essential, to secure data from unapproved access. Data encryption, decryption and key management are the key factors in data protection. It is very important to have the right data security solution to meet the challenging threats. Cryptosystem implementation and random number generators are crucial for Cryptosystem applications such as security applications, space applications, military applications and smart cards et al. In this paper, we present the implementation of hybrid cryptosystem based on the True Random number Generator, pseudo Random number Generator and whitening the data by using the ASIC design flow.

In cryptography, one-time pad (OTP) is claimed to be the perfect secrecy algorithm in several works if all of its features are applied correctly. Its secrecy depends mostly on random keys, which must be truly random and unpredictable. Random number generators are used in key generation. In Psuedo Random Number Generator (PRNG), the possibility of producing numbers that are predictable and repeated exists. In this study, a proposed method using True Random Number Generator (TRNG) and Fisher-Yates shuffling algorithm are implemented to generate random keys for OTP. Frequency (monobit) test, frequency test within a block, and runs tests are performed and showed that the proposed method produces more random keys. Sufficient confusion and diffusion properties are obtained using Pearson correlation analysis.

In this work, we analyze the feasibility of a physically secure implementation of the quantum-resistant supersingular isogeny Diffie-Hellman (SIDH) protocol. Notably, we analyze the defense against timing attacks, simple power analysis, differential power analysis, and fault attacks. Luckily, the SIDH protocol closely resembles its predecessor, the elliptic curve Diffie-Hellman (ECDH) key exchange. As such, much of the extensive literature in side-channel analysis can also apply to SIDH. In particular, we focus on a hardware implementation that features a true random number generator, ALU, and controller. SIDH is composed of two rounds containing a double-point multiplication to generate a secret kernel point and an isogeny over that kernel to arrive at a new elliptic curve isomorphism. To protect against simple power analysis and timing attacks, we recommend a constant-time implementation with Fermat's little theorem inversion. Differential power analysis targets the power output of the SIDH core over many runs. As such, we recommend scaling the base points by secret scalars so that each iteration has a unique power signature. Further, based on recent oracle attacks on SIDH, we cannot recommend the use of static keys from both parties. The goal of this paper is to analyze the tradeoffs in elliptic curve theory to produce a cryptographically and physically secure implementation of SIDH.

Random number generator is an important building block for many cryptographic primitives and protocols. Random numbers are used to initialize key bits, nonces and initialization vectors and seed pseudo-random number generators. Physical Unclonable Functions (PUFs) are a popular security primitive in cryptographic systems used for authentication, secure key storage and so on. PUFs have nature properties of unpredictability and uniqueness which is very suitable to be served as a source of randomness. In this paper we propose a new design of a true random number generator based on ring oscillator PUFs. It utilizes a self-feedback mechanism between the response and challenge of PUFs and some simple operations, mainly addition, rotation and xor, on the output of PUFs to generate truly random bits. Our design is very simple and easy to be implemented while achieving good randomness. Experiment results verified the good quality of bits generated by our design.

The transition effect ring oscillator (TERO) based true random number generator (TRNG) was proposed by Varchola and Drutarovsky in 2010. There were several stochastic models for this advanced TRNG based on ring oscillator. This paper proposed an improved TERO based TRNG and implements both on Altera Cyclone series FPGA platform and on a 0.13um CMOS ASIC process. FPGA experimental results show that this balanced TERO TRNG is in good performance as the experimental data results past the national institute of standards and technology (NIST) test in 1M bit/s. The TRNG is feasible for a security SoC.