Biblio

We propose a methodology for the simulation of electrostatic confinement wells in transistors at cryogenic temperatures. This is considered in the context of 22-nm fully depleted silicon-on-insulator transistors due to their potential for imple-menting quantum bits in scalable quantum computing systems. To overcome thermal fluctuations and improve decoherence times in most quantum bit implementations, they must be operated at cryogenic temperatures. We review the dominant sources of electric field at these low temperatures, including material interface work function differences and trapped interface charges. Intrinsic generation and dopant ionisation are shown to be negligible at cryogenic temperatures when using a mode of operation suitable for confinement. We propose studying cryogenic electrostatic confinement wells in transistors using a finite-element model simulation, and decoupling carrier transport generated fields.

The effects of quantum confinement on the charge distribution in planar Double-Gate (DG) SOI (Siliconon-Insulator) MOSFETs were examined, for sub-10 nm SOI film thicknesses (tsi $łeq$ 10 nm), by modeling the potential experienced by the charge carriers as that of an an-harmonic oscillator potential, consistent with the inherent structural symmetry of nanoscale symmetric DGSOI MOSFETs. By solving the 1-D Poisson's equation using this potential, the results obtained were validated through comparisons with TCAD simulations. The present model satisfactorily predicted the electron density and channel charge density for a wide range of SOI channel thicknesses and gate voltages.

State-of-the-art convolutional neural networks (ConvNets) are now able to achieve near human performance on a wide range of classification tasks. Unfortunately, current hardware implementations of ConvNets are memory power intensive, prohibiting deployment in low-power embedded systems and IoE platforms. One method of reducing memory power is to exploit the error resilience of ConvNets and accept bit errors under reduced supply voltages. In this paper, we extensively study the effectiveness of this idea and show that further savings are possible by injecting bit errors during ConvNet training. Measurements on an 8KB SRAM in 28nm UTBB FD-SOI CMOS demonstrate supply voltage reduction of 310mV, which results in up to 5.4× leakage power reduction and up to 2.9× memory access power reduction at 99% of floating-point classification accuracy, with no additional hardware cost. To our knowledge, this is the first silicon-validated study on the effect of bit errors in ConvNets.