Biblio

Differential Power Analysis (DPA) attacks were shown to be effective in recovering the secret key information from a variety cryptographic systems. In response, several design methods, ranging from the cell level to the algorithmic level, have been proposed to defend against DPA attacks. Cell level solutions depend on DPA resistant cell designs which attempt to minimize power variance during transitions while minimizing area and power consumption. In this paper, we discuss how a differential circuit design style is incorporated into a COTS tool set, resulting in a fully automated synthesis system DPA resistant integrated circuits. Based on the Secure Differential Multiplexer Logic (SDMLp), this system can be used to synthesize complete cryptographic processors which provide strong defense against DPA while minimizing area and power overhead. We discuss how both combinational and sequential cells are incorporated in the cell library. We show the effectiveness of the tool chain by using it to automatically synthesize the layouts, from RT level Verilog specifications, of both the DES and AES encryption ICs in 90nm CMOS. In each case, we present experimental data to demonstrate DPA attack resistance and area, power and performance overhead and compare these with circuits synthesized in another differential logic called MDPL as well as standard CMOS synthesis results.

The core operation of all cryptosystems based on Elliptic Curve Cryptography is Elliptic Curve Point Multiplication. Depending on implementation it can be vulnerable to different Side Channel Analysis attacks exploiting information leakage, such as power consumption or execution time. Multiple countermeasures against these attacks have been developed over time, each having different impact on parameters of the cryptosystem. This paper summarizes popular countermeasures for simple and differential power analysis attacks on Elliptic Curve cryptosystems. Presented secure algorithms were implemented in Verilog hardware description language and synthesized to logic gates for power trace generation.