Biblio
Filters: Keyword is FPGA based IP protection scheme [Clear All Filters]
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2018. FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function. NAECON 2018 - IEEE National Aerospace and Electronics Conference. :105–108.
IP piracy, reverse engineering, and tampering with FPGA based IP is increasing over time. ROPUF based IP obfuscation can provide a feasible solution. In this paper, a novel approach of FPGA IP obfuscation is implemented using Ring Oscillator based Physical Unclonable Function (ROPUF) and random logic gates. This approach provides a lock and key mechanism as well as authentication of FPGA based designs to protect from security threats. Using the Xilinx ISE design tools and ISCAS 89 benchmarks we have designed a secure FPGA based IP protection scheme with an average of 15% area and 10% of power overhead.