| Title | FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function |
| Publication Type | Conference Paper |
| Year of Publication | 2018 |
| Authors | Hazari, N. A., Alsulami, F., Niamat, M. |
| Conference Name | NAECON 2018 - IEEE National Aerospace and Electronics Conference |
| Keywords | composability, cryptography, field programmable gate arrays, FPGA, FPGA based designs, FPGA based IP protection scheme, FPGA IP obfuscation, hardware obfuscation, IP obfuscation, IP piracy, logic design, Logic gates, logic obfuscation, Oscillators, policy-based governance, pubcrawl, PUF, Resiliency, Ring Oscillator, ring oscillator based physical unclonable function, ring oscillator physical unclonable function |
| Abstract | IP piracy, reverse engineering, and tampering with FPGA based IP is increasing over time. ROPUF based IP obfuscation can provide a feasible solution. In this paper, a novel approach of FPGA IP obfuscation is implemented using Ring Oscillator based Physical Unclonable Function (ROPUF) and random logic gates. This approach provides a lock and key mechanism as well as authentication of FPGA based designs to protect from security threats. Using the Xilinx ISE design tools and ISCAS 89 benchmarks we have designed a secure FPGA based IP protection scheme with an average of 15% area and 10% of power overhead. |
| DOI | 10.1109/NAECON.2018.8556746 |
| Citation Key | hazari_fpga_2018 |
FPGA IP Obfuscation Using Ring Oscillator Physical Unclonable Function