CFP - 8th HiPEAC Workshop on Reconfigurable Computing

http://www.cad.polito.it/research/!_EVENTS/WRC_2014/WRC_2014_-_Home_Page.html

The main purpose of this workshop is to encourage the submission of work-in-progress in the topics covered by the call, thus providing quick and valuable feedback. As such we do not provide formal proceedings. Informal proceedings will be provided in an USB stick to all participants including all material relevant to the conference and the related events. We encourage authors of papers who want to immediately timestamp their idea to forward their paper to HiPEAC tech-report, after presentation at our workshop.

- Radiation tolerant FPGA architecture

- Single Event Effects aware Configurable Logic Blocks

- Single Event Upsets mitigation solutions for FPGA

- Dynamic reconfigurable computing for space

- Remote FPGA configuration for space applications

- Fault tolerant reconfigurable systems

- Self-based reconfiguration FPGA for space

- Design tools for SRAM and non-volatile FPGA for space and avionics

- Novel architectures (logic blocks, interconnects, I/O)

- Reconfigurable fabrics combined with dedicated system blocks (DSP, processors, memory etc.)

- Memory issues: adaptivity, coherence, latency tolerance

- Multicore support, resource sharing support

- Low power reconfigurable architectures

- Networks on chip tailored for reconfigurable architectures

- Dynamic and run-time reconfiguration

- Evolvable hardware and self-adaptive computing

- Defect and fault tolerance

- System level design and HW/SW co-design

- Static and dynamic power efficiency

- Modeling, optimization, technology mapping and design verification

- Design and debug of reconfigurable systems

- Testing, verification and benchmarking

- Dedicated compilers and high-level languages

- Operating system support for reconfigurability

- Impact of reconfigurable hardware on real-time performance

- Adaptive and bio inspired applications

- Domain-specific applications, e.g. multimedia, bioinformatics, cryptography and more

- High-performance, high reliability and/or power-efficient application acceleration

- Rapid prototyping

Authors are invited to electronically submit papers with a maximum length of 10 pages in Springer LNCS format.

This workshop is co-located with, and followed by, HiPEAC 2014 - International Conference on High Performance Embedded Architectures & Compilers, www.hipeac.net/conference/.

Mario Porrmann

Yannis Papaefstathiou

Marco D. Santambrogio

Theocharis Thecoharides

Luca Sterpone

Technical Program Committee
Jose L. Ayala, Universidad Complutense de Madrid, Spain
Sandro Bartolini, University of Siena, Italy
Christophe Bobda, University of Arkansas, USA
Luca Cassano, University of Pisa
Daniel Chillet, Universite Rennes, France
Eduardo De La Torre, Universidad Politecnica de Madrid
Carlo Galuzzi, TU Delft, The Netherlands
Pao-Ann Hsiung, National Chung Cheng University, Taiwan
Michael Hubner, University of Karlsruhe, Germany
Costas Kyriacou, Frederick University, Cyprus
Andreas Koch, TU Darmstadt, Germany
Dirk Koch, University of Oslo, Norway
Seda Ogrenci Memik, Northwestern University, USA
Gianluca Palermo, Politecnico di Milano, Italy
Christian Pilato, Politecnico di Milano, Italy
Dionisios N. Pnevmatikatos, Technical University of Crete, Greece
Dan Poznanovic, Custom Engineering Cray Inc., USA
Vincenzo Rana, Politecnico di Milano, Italy
Paolo Rech, UFRGS, Brazil
Luca Sterpone, Politecnico di Torino, Italy
Theocharis Thecoharides, University of Cyprus
Marco D. Santambrogio, Politecnico di Milano, Italy
Leonel Sousa, University of Lisbon, Portugal
Dirk Stroobandt, Ghent University, Belgium
Dimitrios Soudris, NTUA, Greece
Ioannis Sourdis, TU Delft, The Netherlands
Pedro Trancoso, University of Cyprus, Cyprus
David Thomas, Imperial College, UK
Theo Ungerer, University of Augsburg, Germany
Stephan Wong, TU Delft, The Netherlands