Biblio

Filters: Author is Navabi, Zainalabedin  [Clear All Filters]
2020-10-06
Yousefzadeh, Saba, Basharkhah, Katayoon, Nosrati, Nooshin, Sadeghi, Rezgar, Raik, Jaan, Jenihhin, Maksim, Navabi, Zainalabedin.  2019.  An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements. 2019 IEEE East-West Design Test Symposium (EWDTS). :1—6.

Hardware implementation of many of today's applications such as those in automotive, telecommunication, bio, and security, require heavy repeated computations, and concurrency in the execution of these computations. These requirements are not easily satisfied by existing embedded systems. This paper proposes an embedded system architecture that is enhanced by an array of accelerators, and a bussing system that enables concurrency in operation of accelerators. This architecture is statically configurable to configure it for performing a specific application. The embedded system architecture and architecture of the configurable accelerators are discussed in this paper. A case study examines an automotive application running on our proposed system.