A 60Gbps DPI Prototype Based on Memory-Centric FPGA
| Title | A 60Gbps DPI Prototype Based on Memory-Centric FPGA |
| Publication Type | Conference Paper |
| Year of Publication | 2016 |
| Authors | Su, Jinshu, Chen, Shuhui, Han, Biao, Xu, Chengcheng, Wang, Xin |
| Conference Name | Proceedings of the 2016 ACM SIGCOMM Conference |
| Publisher | ACM |
| Conference Location | New York, NY, USA |
| ISBN Number | 978-1-4503-4193-6 |
| Keywords | composability, deep packet inspection, DPI, hierarchical memory, Metrics, pubcrawl, Scalability, string matching |
| Abstract | Deep packet inspection (DPI) is widely used in content-aware network applications to detect string features. It is of vital importance to improve the DPI performance due to the ever-increasing link speed. In this demo, we propose a novel DPI architecture with a hierarchy memory structure and parallel matching engines based on memory-centric FPGA. The implemented DPI prototype is able to provide up to 60Gbps full-text string matching throughput and fast rules update speed. |
| URL | http://doi.acm.org/10.1145/2934872.2959079 |
| DOI | 10.1145/2934872.2959079 |
| Citation Key | su_60gbps_2016 |